周琰杰 (Zhou Yanjie) 34c522a07c MIPS: CI20: Add second percpu timer for SMP. ... 1.Add a new TCU channel as the percpu timer of core1, this is to prepare for the subsequent SMP support. The newly added channel will not adversely affect the current single-core state. 2.Adjust the position of TCU node to make it consistent with the order in jz4780.dtsi file. Tested-by: Nikolaus Schaller <hns@goldelico.com> # on CI20 Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Acked-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>		2021-06-30 14:37:16 +02:00
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compressed	MIPS: boot: Support specifying UART port on Ingenic SoCs	2021-06-01 11:44:47 +02:00
dts	MIPS: CI20: Add second percpu timer for SMP.	2021-06-30 14:37:16 +02:00
tools
.gitignore
ecoff.h
elf2ecoff.c
Makefile