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3f2bedabb6
The boot-time detection of futex_atomic_cmpxchg_inatomic() has a bug on some 32-bit arm builds, and Thomas Gleixner suggested that setting CONFIG_HAVE_FUTEX_CMPXCHG would avoid the problem, as it is always present anyway. Looking into which other architectures could do the same showed that almost all architectures have it, the exceptions being: - some old 32-bit MIPS uniprocessor cores without ll/sc - one xtensa variant with no SMP - 32-bit SPARC when built for SMP Fix MIPS And Xtensa by rearranging the generic code to let it be used as a fallback. For SPARC, the SMP definition just ends up turning off futex anyway, so this can be done at Kconfig time instead. Note that sparc32 glibc requires the CASA instruction for its mutexes anyway, which is only available when running on SPARCv9 or LEON CPUs, but needs to be implemented in the sparc32 kernel for those. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Max Filippov <jcmvbkbc@gmail.com> Acked-by: Geert Uytterhoeven <geert@linux-m68k.org> Acked-by: Rich Felker <dalias@libc.org> Link: https://lore.kernel.org/r/20211026100432.1730393-1-arnd@kernel.org
211 lines
5.4 KiB
C
211 lines
5.4 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (c) 2006 Ralf Baechle (ralf@linux-mips.org)
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*/
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#ifndef _ASM_FUTEX_H
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#define _ASM_FUTEX_H
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#ifdef __KERNEL__
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#include <linux/futex.h>
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#include <linux/uaccess.h>
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#include <asm/asm-eva.h>
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#include <asm/barrier.h>
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#include <asm/compiler.h>
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#include <asm/errno.h>
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#include <asm/sync.h>
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#include <asm/war.h>
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#define arch_futex_atomic_op_inuser arch_futex_atomic_op_inuser
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#define futex_atomic_cmpxchg_inatomic futex_atomic_cmpxchg_inatomic
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#include <asm-generic/futex.h>
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#define __futex_atomic_op(op, insn, ret, oldval, uaddr, oparg) \
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{ \
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if (cpu_has_llsc && IS_ENABLED(CONFIG_WAR_R10000_LLSC)) { \
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__asm__ __volatile__( \
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" .set push \n" \
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" .set noat \n" \
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" .set push \n" \
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" .set arch=r4000 \n" \
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"1: ll %1, %4 # __futex_atomic_op \n" \
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" .set pop \n" \
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" " insn " \n" \
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" .set arch=r4000 \n" \
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"2: sc $1, %2 \n" \
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" beqzl $1, 1b \n" \
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__stringify(__WEAK_LLSC_MB) " \n" \
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"3: \n" \
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" .insn \n" \
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" .set pop \n" \
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" .section .fixup,\"ax\" \n" \
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"4: li %0, %6 \n" \
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" j 3b \n" \
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" .previous \n" \
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" .section __ex_table,\"a\" \n" \
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" "__UA_ADDR "\t1b, 4b \n" \
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" "__UA_ADDR "\t2b, 4b \n" \
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" .previous \n" \
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: "=r" (ret), "=&r" (oldval), \
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"=" GCC_OFF_SMALL_ASM() (*uaddr) \
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: "0" (0), GCC_OFF_SMALL_ASM() (*uaddr), "Jr" (oparg), \
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"i" (-EFAULT) \
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: "memory"); \
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} else if (cpu_has_llsc) { \
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__asm__ __volatile__( \
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" .set push \n" \
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" .set noat \n" \
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" .set push \n" \
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" .set "MIPS_ISA_ARCH_LEVEL" \n" \
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" " __SYNC(full, loongson3_war) " \n" \
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"1: "user_ll("%1", "%4")" # __futex_atomic_op\n" \
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" .set pop \n" \
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" " insn " \n" \
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" .set "MIPS_ISA_ARCH_LEVEL" \n" \
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"2: "user_sc("$1", "%2")" \n" \
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" beqz $1, 1b \n" \
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__stringify(__WEAK_LLSC_MB) " \n" \
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"3: \n" \
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" .insn \n" \
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" .set pop \n" \
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" .section .fixup,\"ax\" \n" \
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"4: li %0, %6 \n" \
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" j 3b \n" \
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" .previous \n" \
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" .section __ex_table,\"a\" \n" \
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" "__UA_ADDR "\t1b, 4b \n" \
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" "__UA_ADDR "\t2b, 4b \n" \
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" .previous \n" \
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: "=r" (ret), "=&r" (oldval), \
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"=" GCC_OFF_SMALL_ASM() (*uaddr) \
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: "0" (0), GCC_OFF_SMALL_ASM() (*uaddr), "Jr" (oparg), \
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"i" (-EFAULT) \
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: "memory"); \
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} else { \
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/* fallback for non-SMP */ \
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ret = arch_futex_atomic_op_inuser_local(op, oparg, oval,\
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uaddr); \
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}
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static inline int
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arch_futex_atomic_op_inuser(int op, int oparg, int *oval, u32 __user *uaddr)
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{
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int oldval = 0, ret;
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if (!access_ok(uaddr, sizeof(u32)))
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return -EFAULT;
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switch (op) {
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case FUTEX_OP_SET:
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__futex_atomic_op(op, "move $1, %z5", ret, oldval, uaddr, oparg);
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break;
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case FUTEX_OP_ADD:
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__futex_atomic_op(op, "addu $1, %1, %z5",
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ret, oldval, uaddr, oparg);
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break;
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case FUTEX_OP_OR:
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__futex_atomic_op(op, "or $1, %1, %z5",
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ret, oldval, uaddr, oparg);
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break;
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case FUTEX_OP_ANDN:
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__futex_atomic_op(op, "and $1, %1, %z5",
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ret, oldval, uaddr, ~oparg);
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break;
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case FUTEX_OP_XOR:
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__futex_atomic_op(op, "xor $1, %1, %z5",
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ret, oldval, uaddr, oparg);
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break;
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default:
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ret = -ENOSYS;
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}
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if (!ret)
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*oval = oldval;
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return ret;
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}
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static inline int
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futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
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u32 oldval, u32 newval)
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{
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int ret = 0;
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u32 val;
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if (!access_ok(uaddr, sizeof(u32)))
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return -EFAULT;
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if (cpu_has_llsc && IS_ENABLED(CONFIG_WAR_R10000_LLSC)) {
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__asm__ __volatile__(
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"# futex_atomic_cmpxchg_inatomic \n"
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" .set push \n"
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" .set noat \n"
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" .set push \n"
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" .set arch=r4000 \n"
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"1: ll %1, %3 \n"
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" bne %1, %z4, 3f \n"
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" .set pop \n"
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" move $1, %z5 \n"
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" .set arch=r4000 \n"
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"2: sc $1, %2 \n"
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" beqzl $1, 1b \n"
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__stringify(__WEAK_LLSC_MB) " \n"
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"3: \n"
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" .insn \n"
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" .set pop \n"
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" .section .fixup,\"ax\" \n"
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"4: li %0, %6 \n"
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" j 3b \n"
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" .previous \n"
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" .section __ex_table,\"a\" \n"
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" "__UA_ADDR "\t1b, 4b \n"
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" "__UA_ADDR "\t2b, 4b \n"
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" .previous \n"
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: "+r" (ret), "=&r" (val), "=" GCC_OFF_SMALL_ASM() (*uaddr)
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: GCC_OFF_SMALL_ASM() (*uaddr), "Jr" (oldval), "Jr" (newval),
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"i" (-EFAULT)
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: "memory");
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} else if (cpu_has_llsc) {
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__asm__ __volatile__(
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"# futex_atomic_cmpxchg_inatomic \n"
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" .set push \n"
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" .set noat \n"
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" .set push \n"
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" .set "MIPS_ISA_ARCH_LEVEL" \n"
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" " __SYNC(full, loongson3_war) " \n"
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"1: "user_ll("%1", "%3")" \n"
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" bne %1, %z4, 3f \n"
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" .set pop \n"
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" move $1, %z5 \n"
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" .set "MIPS_ISA_ARCH_LEVEL" \n"
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"2: "user_sc("$1", "%2")" \n"
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" beqz $1, 1b \n"
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"3: " __SYNC_ELSE(full, loongson3_war, __WEAK_LLSC_MB) "\n"
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" .insn \n"
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" .set pop \n"
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" .section .fixup,\"ax\" \n"
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"4: li %0, %6 \n"
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" j 3b \n"
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" .previous \n"
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" .section __ex_table,\"a\" \n"
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" "__UA_ADDR "\t1b, 4b \n"
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" "__UA_ADDR "\t2b, 4b \n"
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" .previous \n"
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: "+r" (ret), "=&r" (val), "=" GCC_OFF_SMALL_ASM() (*uaddr)
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: GCC_OFF_SMALL_ASM() (*uaddr), "Jr" (oldval), "Jr" (newval),
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"i" (-EFAULT)
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: "memory");
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} else {
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return futex_atomic_cmpxchg_inatomic_local(uval, uaddr, oldval, newval);
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}
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*uval = val;
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return ret;
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}
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#endif
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#endif /* _ASM_FUTEX_H */
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