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407cd87c54
The x86 and ia64 implementations of arch_acpi_processor_init_pdc() are almost exactly the same. The only difference is in what bits they set in obj_list buffer. Combine the boilerplate memory management code, and leave the arch-specific bit twiddling in separate implementations. Cc: Tony Luck <tony.luck@intel.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Ingo Molnar <mingo@redhat.com> Cc: "H. Peter Anvin" <hpa@zytor.com> Signed-off-by: Alex Chiang <achiang@hp.com> Signed-off-by: Len Brown <len.brown@intel.com>
67 lines
1.5 KiB
C
67 lines
1.5 KiB
C
/*
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* Copyright (C) 2005 Intel Corporation
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* Venkatesh Pallipadi <venkatesh.pallipadi@intel.com>
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* - Added _PDC for platforms with Intel CPUs
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/acpi.h>
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#include <acpi/processor.h>
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#include <asm/acpi.h>
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static void init_intel_pdc(struct acpi_processor *pr, struct cpuinfo_x86 *c)
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{
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u32 *buf = (u32 *)pr->pdc->pointer->buffer.pointer;
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buf[0] = ACPI_PDC_REVISION_ID;
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buf[1] = 1;
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buf[2] = ACPI_PDC_C_CAPABILITY_SMP;
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/*
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* The default of PDC_SMP_T_SWCOORD bit is set for intel x86 cpu so
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* that OSPM is capable of native ACPI throttling software
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* coordination using BIOS supplied _TSD info.
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*/
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buf[2] |= ACPI_PDC_SMP_T_SWCOORD;
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if (cpu_has(c, X86_FEATURE_EST))
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buf[2] |= ACPI_PDC_EST_CAPABILITY_SWSMP;
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if (cpu_has(c, X86_FEATURE_ACPI))
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buf[2] |= ACPI_PDC_T_FFH;
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/*
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* If mwait/monitor is unsupported, C2/C3_FFH will be disabled
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*/
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if (!cpu_has(c, X86_FEATURE_MWAIT))
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buf[2] &= ~(ACPI_PDC_C_C2C3_FFH);
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return;
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}
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/* Initialize _PDC data based on the CPU vendor */
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void arch_acpi_processor_init_pdc(struct acpi_processor *pr)
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{
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struct cpuinfo_x86 *c = &cpu_data(pr->id);
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init_intel_pdc(pr, c);
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return;
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}
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EXPORT_SYMBOL(arch_acpi_processor_init_pdc);
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void arch_acpi_processor_cleanup_pdc(struct acpi_processor *pr)
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{
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if (pr->pdc) {
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kfree(pr->pdc->pointer->buffer.pointer);
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kfree(pr->pdc->pointer);
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kfree(pr->pdc);
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pr->pdc = NULL;
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}
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}
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EXPORT_SYMBOL(arch_acpi_processor_cleanup_pdc);
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