Kishon Vijay Abraham I a660083eb0 PCI: dwc: designware: Add new *ops* for CPU addr fixup ... Some platforms (like dra7xx) require only the least 28 bits of the corresponding 32 bit CPU address to be programmed in the address translation unit. This modified address is stored in io_base/mem_base/ cfg0_base/cfg1_base in dra7xx_pcie_host_init(). While this is okay for host mode where the address range is fixed, device mode requires different addresses to be programmed based on the host buffer address. Add a new ops to get the least 28 bits of the corresponding 32 bit CPU address and invoke it before programming the address translation unit. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Joao Pinto <jpinto@synopsys.com>		2017-04-04 08:30:10 -05:00
..
Kconfig	PCI: dwc: Select PCI_HOST_COMMON for hisi	2017-04-03 16:17:11 -05:00
Makefile
pci-dra7xx.c
pci-exynos.c	PCI: exynos: Initialize elbi_base even when using PHY framework	2017-03-07 12:46:38 -06:00
pci-imx6.c
pci-keystone-dw.c
pci-keystone.c
pci-keystone.h
pci-layerscape.c
pcie-armada8k.c
pcie-artpec6.c	PCI: dwc: Fix dw_pcie_ops NULL pointer dereference	2017-04-04 08:24:25 -05:00
pcie-designware-host.c	PCI: dwc: Fix uninitialized variable in dw_handle_msi_irq()	2017-04-04 08:29:56 -05:00
pcie-designware-plat.c	PCI: dwc: Fix dw_pcie_ops NULL pointer dereference	2017-04-04 08:24:25 -05:00
pcie-designware.c	PCI: dwc: designware: Add new *ops* for CPU addr fixup	2017-04-04 08:30:10 -05:00
pcie-designware.h	PCI: dwc: designware: Add new *ops* for CPU addr fixup	2017-04-04 08:30:10 -05:00
pcie-hisi.c
pcie-qcom.c
pcie-spear13xx.c