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* new gpu support: a405, a640, a650 * dpu: color processing support * mdp5: support for msm8x36 (the thing with a405) * some prep work for per-context pagetables (ie the part that does not depend on in-flight iommu patches) * last but not least, UABI update for submit ioctl to support syncobj (from Bas) -----BEGIN PGP SIGNATURE----- iQIcBAABAgAGBQJe3bDxAAoJEAx081l5xIa+tkoQAIGUxvEgYBQ+S6RvANZAT+Wq 2JZS2JPvExcB3Xe4erI+y7DeIuK2VghQUAcxMWhrDGgU7jKLV7jq09HTKkdE7++4 feLQMZziy3rAN3H6Pe1+72ZI9jAeK7JpvyRxI1nSu1O1JnaZS2rHmCOnBT8yA8sw tHld1b5KUMmgTLR6CcJQYz0qp7p8x5LE8MdWY57Px5AqcnXFf1z/oiYNiCcxK2Jl tEic1b9mvCwvlGWYdu00aavqo7WESj3oWYxtb8MsmVBWjAHtTqrlBY21DyQzgdEu sgc8QAG+zHJ7Ls81INSVfDQ1zrspn/n+yL8efMhQibpMAQqGgt17nF+ZIx50nLMi USg5qBJKgBL2iccooA9QEioFE3tB6Ld8SfcjLGIU7jegi0Fw/KpVPqmUVjKdqrXT qjUKExa4e4pFxOlgbOYc1lIzSLwpGjGpLWbRWj8aee1GyrWRJA0Y9aRo75G6Sr4e SX6807kX+h0IrF1rJzftVKa+KviD9SD4NyAyah6OJvg0FVJnhbO75PmnAkB6GVnQ Jgg7fALjjkANRd8764H2B0pjke6wPDnUNXnh32ei2FWxVfQfIu/qhlJg9cU7TdMf Z2kcHijoRGjAfvddD+oDs3DS58b9o7DHKgsZuLWvh87MpVbv9CynZSh5SgGqqNKR nHajwsRXQc6e/fXT4YzN =hIK6 -----END PGP SIGNATURE----- Merge tag 'drm-next-msm-5.8-2020-06-08' of git://anongit.freedesktop.org/drm/drm Pull drm msm updates from Dave Airlie: "This tree has been in next for a couple of weeks, but Rob missed an arm32 build issue, so I was awaiting the tree with a patch reverted. - new gpu support: a405, a640, a650 - dpu: color processing support - mdp5: support for msm8x36 (the thing with a405) - some prep work for per-context pagetables (ie the part that does not depend on in-flight iommu patches) - last but not least, UABI update for submit ioctl to support syncobj (from Bas)" * tag 'drm-next-msm-5.8-2020-06-08' of git://anongit.freedesktop.org/drm/drm: (30 commits) Revert "drm/msm/dpu: add support for clk and bw scaling for display" drm/msm/a6xx: skip HFI set freq if GMU is powered down drm/msm: Update the MMU helper function APIs drm/msm: Refactor address space initialization drm/msm: Attach the IOMMU device during initialization drm/msm/dpu: dpu_setup_dspp_pcc() can be static drm/msm/a6xx: a6xx_hfi_send_start() can be static drm/msm/a4xx: add a405_registers for a405 device drm/msm/a4xx: add adreno a405 support drm/msm/a6xx: update a6xx_hw_init for A640 and A650 drm/msm/a6xx: enable GMU log drm/msm/a6xx: update pdc/rscc GMU registers for A640/A650 drm/msm/a6xx: A640/A650 GMU firmware path drm/msm/a6xx: HFI v2 for A640 and A650 drm/msm/a6xx: add A640/A650 to gpulist drm/msm/a6xx: use msm_gem for GMU memory objects drm/msm: add internal MSM_BO_MAP_PRIV flag drm/msm: add msm_gem_get_and_pin_iova_range drm/msm: Check for powered down HW in the devfreq callbacks drm/msm/dpu: update bandwidth threshold check ...
262 lines
7.7 KiB
C
262 lines
7.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
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* Copyright (C) 2013 Red Hat
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* Author: Rob Clark <robdclark@gmail.com>
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*/
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#ifndef __DPU_KMS_H__
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#define __DPU_KMS_H__
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#include <drm/drm_drv.h>
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#include "msm_drv.h"
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#include "msm_kms.h"
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#include "msm_mmu.h"
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#include "msm_gem.h"
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#include "dpu_hw_catalog.h"
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#include "dpu_hw_ctl.h"
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#include "dpu_hw_lm.h"
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#include "dpu_hw_interrupts.h"
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#include "dpu_hw_top.h"
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#include "dpu_io_util.h"
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#include "dpu_rm.h"
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#include "dpu_core_perf.h"
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#define DRMID(x) ((x) ? (x)->base.id : -1)
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/**
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* DPU_DEBUG - macro for kms/plane/crtc/encoder/connector logs
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* @fmt: Pointer to format string
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*/
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#define DPU_DEBUG(fmt, ...) \
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do { \
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if (drm_debug_enabled(DRM_UT_KMS)) \
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DRM_DEBUG(fmt, ##__VA_ARGS__); \
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else \
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pr_debug(fmt, ##__VA_ARGS__); \
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} while (0)
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/**
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* DPU_DEBUG_DRIVER - macro for hardware driver logging
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* @fmt: Pointer to format string
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*/
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#define DPU_DEBUG_DRIVER(fmt, ...) \
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do { \
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if (drm_debug_enabled(DRM_UT_DRIVER)) \
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DRM_ERROR(fmt, ##__VA_ARGS__); \
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else \
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pr_debug(fmt, ##__VA_ARGS__); \
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} while (0)
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#define DPU_ERROR(fmt, ...) pr_err("[dpu error]" fmt, ##__VA_ARGS__)
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/**
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* ktime_compare_safe - compare two ktime structures
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* This macro is similar to the standard ktime_compare() function, but
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* attempts to also handle ktime overflows.
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* @A: First ktime value
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* @B: Second ktime value
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* Returns: -1 if A < B, 0 if A == B, 1 if A > B
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*/
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#define ktime_compare_safe(A, B) \
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ktime_compare(ktime_sub((A), (B)), ktime_set(0, 0))
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#define DPU_NAME_SIZE 12
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/*
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* struct dpu_irq_callback - IRQ callback handlers
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* @list: list to callback
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* @func: intr handler
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* @arg: argument for the handler
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*/
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struct dpu_irq_callback {
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struct list_head list;
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void (*func)(void *arg, int irq_idx);
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void *arg;
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};
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/**
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* struct dpu_irq: IRQ structure contains callback registration info
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* @total_irq: total number of irq_idx obtained from HW interrupts mapping
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* @irq_cb_tbl: array of IRQ callbacks setting
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* @enable_counts array of IRQ enable counts
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* @cb_lock: callback lock
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* @debugfs_file: debugfs file for irq statistics
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*/
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struct dpu_irq {
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u32 total_irqs;
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struct list_head *irq_cb_tbl;
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atomic_t *enable_counts;
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atomic_t *irq_counts;
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spinlock_t cb_lock;
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};
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struct dpu_kms {
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struct msm_kms base;
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struct drm_device *dev;
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int core_rev;
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struct dpu_mdss_cfg *catalog;
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/* io/register spaces: */
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void __iomem *mmio, *vbif[VBIF_MAX], *reg_dma;
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unsigned long mmio_len, vbif_len[VBIF_MAX], reg_dma_len;
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struct regulator *vdd;
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struct regulator *mmagic;
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struct regulator *venus;
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struct dpu_hw_intr *hw_intr;
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struct dpu_irq irq_obj;
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struct dpu_core_perf perf;
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/*
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* Global private object state, Do not access directly, use
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* dpu_kms_global_get_state()
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*/
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struct drm_modeset_lock global_state_lock;
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struct drm_private_obj global_state;
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struct dpu_rm rm;
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bool rm_init;
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struct dpu_hw_vbif *hw_vbif[VBIF_MAX];
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struct dpu_hw_mdp *hw_mdp;
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bool has_danger_ctrl;
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struct platform_device *pdev;
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bool rpm_enabled;
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struct dss_module_power mp;
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/* reference count bandwidth requests, so we know when we can
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* release bandwidth. Each atomic update increments, and frame-
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* done event decrements. Additionally, for video mode, the
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* reference is incremented when crtc is enabled, and decremented
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* when disabled.
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*/
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atomic_t bandwidth_ref;
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};
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struct vsync_info {
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u32 frame_count;
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u32 line_count;
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};
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#define to_dpu_kms(x) container_of(x, struct dpu_kms, base)
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#define to_dpu_global_state(x) container_of(x, struct dpu_global_state, base)
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/* Global private object state for tracking resources that are shared across
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* multiple kms objects (planes/crtcs/etc).
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*/
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struct dpu_global_state {
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struct drm_private_state base;
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uint32_t pingpong_to_enc_id[PINGPONG_MAX - PINGPONG_0];
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uint32_t mixer_to_enc_id[LM_MAX - LM_0];
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uint32_t ctl_to_enc_id[CTL_MAX - CTL_0];
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uint32_t intf_to_enc_id[INTF_MAX - INTF_0];
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uint32_t dspp_to_enc_id[DSPP_MAX - DSPP_0];
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};
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struct dpu_global_state
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*dpu_kms_get_existing_global_state(struct dpu_kms *dpu_kms);
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struct dpu_global_state
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*__must_check dpu_kms_get_global_state(struct drm_atomic_state *s);
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/**
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* Debugfs functions - extra helper functions for debugfs support
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*
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* Main debugfs documentation is located at,
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*
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* Documentation/filesystems/debugfs.rst
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*
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* @dpu_debugfs_setup_regset32: Initialize data for dpu_debugfs_create_regset32
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* @dpu_debugfs_create_regset32: Create 32-bit register dump file
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* @dpu_debugfs_get_root: Get root dentry for DPU_KMS's debugfs node
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*/
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/**
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* Companion structure for dpu_debugfs_create_regset32. Do not initialize the
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* members of this structure explicitly; use dpu_debugfs_setup_regset32 instead.
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*/
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struct dpu_debugfs_regset32 {
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uint32_t offset;
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uint32_t blk_len;
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struct dpu_kms *dpu_kms;
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};
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/**
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* dpu_debugfs_setup_regset32 - Initialize register block definition for debugfs
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* This function is meant to initialize dpu_debugfs_regset32 structures for use
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* with dpu_debugfs_create_regset32.
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* @regset: opaque register definition structure
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* @offset: sub-block offset
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* @length: sub-block length, in bytes
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* @dpu_kms: pointer to dpu kms structure
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*/
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void dpu_debugfs_setup_regset32(struct dpu_debugfs_regset32 *regset,
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uint32_t offset, uint32_t length, struct dpu_kms *dpu_kms);
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/**
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* dpu_debugfs_create_regset32 - Create register read back file for debugfs
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*
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* This function is almost identical to the standard debugfs_create_regset32()
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* function, with the main difference being that a list of register
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* names/offsets do not need to be provided. The 'read' function simply outputs
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* sequential register values over a specified range.
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*
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* Similar to the related debugfs_create_regset32 API, the structure pointed to
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* by regset needs to persist for the lifetime of the created file. The calling
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* code is responsible for initialization/management of this structure.
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*
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* The structure pointed to by regset is meant to be opaque. Please use
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* dpu_debugfs_setup_regset32 to initialize it.
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*
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* @name: File name within debugfs
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* @mode: File mode within debugfs
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* @parent: Parent directory entry within debugfs, can be NULL
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* @regset: Pointer to persistent register block definition
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*/
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void dpu_debugfs_create_regset32(const char *name, umode_t mode,
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void *parent, struct dpu_debugfs_regset32 *regset);
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/**
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* dpu_debugfs_get_root - Return root directory entry for KMS's debugfs
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*
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* The return value should be passed as the 'parent' argument to subsequent
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* debugfs create calls.
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*
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* @dpu_kms: Pointer to DPU's KMS structure
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*
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* Return: dentry pointer for DPU's debugfs location
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*/
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void *dpu_debugfs_get_root(struct dpu_kms *dpu_kms);
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/**
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* DPU info management functions
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* These functions/definitions allow for building up a 'dpu_info' structure
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* containing one or more "key=value\n" entries.
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*/
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#define DPU_KMS_INFO_MAX_SIZE 4096
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/**
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* Vblank enable/disable functions
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*/
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int dpu_enable_vblank(struct msm_kms *kms, struct drm_crtc *crtc);
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void dpu_disable_vblank(struct msm_kms *kms, struct drm_crtc *crtc);
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void dpu_kms_encoder_enable(struct drm_encoder *encoder);
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/**
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* dpu_kms_get_clk_rate() - get the clock rate
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* @dpu_kms: poiner to dpu_kms structure
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* @clock_name: clock name to get the rate
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*
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* Return: current clock rate
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*/
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u64 dpu_kms_get_clk_rate(struct dpu_kms *dpu_kms, char *clock_name);
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#endif /* __dpu_kms_H__ */
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