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0095456646
The manufacturer of this board, ships it with various SPI NOR chips and
increments U-Boot bootloader version along the time. There is no way to
tell which is placed on the board since no revision bump takes place.
This creates two issues.
The first, cosmetic. Since the NOR chip may differ, there's message on
boot stating that kernel expected w25q32dw and found different one. To
correct this, remove optional device-specific compatible string. Being
here lets replace bogus "spi-flash" compatible string with proper one.
The second is linked to partitions layout, it changed after commit:
81e7251252 ("arm64: mvebu: config: move env to the end of the 4MB boot
device") in Marvells downstream U-Boot fork [1], shifting environment
location to the end of boot device. Since the new boards will have U-Boot
with this change, it'll lead to improper results writing or reading from
these partitions. We can't tell if users will update bootloader to recent
version provided on manufacturer website, so lets drop partitons layout.
1. https://github.com/MarvellEmbeddedProcessors/u-boot-marvell.git
Signed-off-by: Tomasz Maciej Nowak <tmn505@gmail.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
202 lines
3.5 KiB
Text
202 lines
3.5 KiB
Text
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Device Tree file for Globalscale Marvell ESPRESSOBin Board
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* Copyright (C) 2016 Marvell
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*
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* Romain Perier <romain.perier@free-electrons.com>
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*
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*/
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/*
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* Schematic available at http://espressobin.net/wp-content/uploads/2017/08/ESPRESSObin_V5_Schematics.pdf
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*/
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/dts-v1/;
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#include <dt-bindings/gpio/gpio.h>
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#include "armada-372x.dtsi"
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/ {
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model = "Globalscale Marvell ESPRESSOBin Board";
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compatible = "globalscale,espressobin", "marvell,armada3720", "marvell,armada3710";
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chosen {
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stdout-path = "serial0:115200n8";
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};
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memory@0 {
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device_type = "memory";
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reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
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};
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vcc_sd_reg1: regulator {
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compatible = "regulator-gpio";
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regulator-name = "vcc_sd1";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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gpios = <&gpionb 4 GPIO_ACTIVE_HIGH>;
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gpios-states = <0>;
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states = <1800000 0x1
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3300000 0x0>;
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enable-active-high;
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};
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};
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/* J9 */
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&pcie0 {
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status = "okay";
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phys = <&comphy1 0>;
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pinctrl-names = "default";
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pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>;
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};
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/* J6 */
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&sata {
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status = "okay";
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phys = <&comphy2 0>;
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phy-names = "sata-phy";
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};
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/* J1 */
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&sdhci1 {
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wp-inverted;
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bus-width = <4>;
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cd-gpios = <&gpionb 3 GPIO_ACTIVE_LOW>;
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marvell,pad-type = "sd";
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vqmmc-supply = <&vcc_sd_reg1>;
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pinctrl-names = "default";
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pinctrl-0 = <&sdio_pins>;
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status = "okay";
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};
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/* U11 */
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&sdhci0 {
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non-removable;
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bus-width = <8>;
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mmc-ddr-1_8v;
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mmc-hs400-1_8v;
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marvell,xenon-emmc;
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marvell,xenon-tun-count = <9>;
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marvell,pad-type = "fixed-1-8v";
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pinctrl-names = "default";
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pinctrl-0 = <&mmc_pins>;
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/*
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* This eMMC is not populated on all boards, so disable it by
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* default and let the bootloader enable it, if it is present
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*/
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status = "disabled";
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};
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&spi0 {
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status = "okay";
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flash@0 {
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reg = <0>;
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compatible = "jedec,spi-nor";
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spi-max-frequency = <104000000>;
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m25p,fast-read;
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};
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};
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/* Exported on the micro USB connector J5 through an FTDI */
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&uart0 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart1_pins>;
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status = "okay";
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};
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/*
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* Connector J17 and J18 expose a number of different features. Some pins are
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* multiplexed. This is the case for instance for the following features:
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* - UART1 (pin 24 = RX, pin 26 = TX). See armada-3720-db.dts for an example of
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* how to enable it. Beware that the signals are 1.8V TTL.
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* - I2C
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* - SPI
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* - MMC
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*/
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/* J7 */
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&usb3 {
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status = "okay";
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};
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/* J8 */
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&usb2 {
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status = "okay";
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};
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&mdio {
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switch0: switch0@1 {
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compatible = "marvell,mv88e6085";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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dsa,member = <0 0>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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label = "cpu";
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ethernet = <ð0>;
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phy-mode = "rgmii-id";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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port@1 {
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reg = <1>;
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label = "wan";
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phy-handle = <&switch0phy0>;
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};
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port@2 {
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reg = <2>;
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label = "lan0";
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phy-handle = <&switch0phy1>;
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};
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port@3 {
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reg = <3>;
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label = "lan1";
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phy-handle = <&switch0phy2>;
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};
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};
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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switch0phy0: switch0phy0@11 {
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reg = <0x11>;
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};
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switch0phy1: switch0phy1@12 {
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reg = <0x12>;
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};
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switch0phy2: switch0phy2@13 {
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reg = <0x13>;
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};
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};
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};
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};
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ð0 {
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pinctrl-names = "default";
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pinctrl-0 = <&rgmii_pins>, <&smi_pins>;
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phy-mode = "rgmii-id";
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status = "okay";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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