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To prevent an infinite loop in mc146818_get_time(), commit211e5db19d("rtc: mc146818: Detect and handle broken RTCs") added a check for RTC availability. Together with a later fix, it checked if bit 6 in register 0x0d is cleared. This, however, caused a false negative on a motherboard with an AMD SB710 southbridge; according to the specification [1], bit 6 of register 0x0d of this chipset is a scratchbit. This caused a regression in Linux 5.11 - the RTC was determined broken by the kernel and not used by rtc-cmos.c [3]. This problem was also reported in Fedora [4]. As a better alternative, check whether the UIP ("Update-in-progress") bit is set for longer then 10ms. If that is the case, then apparently the RTC is either absent (and all register reads return 0xff) or broken. Also limit the number of loop iterations in mc146818_get_time() to 10 to prevent an infinite loop there. The functions mc146818_get_time() and mc146818_does_rtc_work() will be refactored later in this patch series, in order to fix a separate problem with reading / setting the RTC alarm time. This is done so to avoid a confusion about what is being fixed when. In a previous approach to this problem, I implemented a check whether the RTC_HOURS register contains a value <= 24. This, however, sometimes did not work correctly on my Intel Kaby Lake laptop. According to Intel's documentation [2], "the time and date RAM locations (0-9) are disconnected from the external bus" during the update cycle so reading this register without checking the UIP bit is incorrect. [1] AMD SB700/710/750 Register Reference Guide, page 308, https://developer.amd.com/wordpress/media/2012/10/43009_sb7xx_rrg_pub_1.00.pdf [2] 7th Generation Intel ® Processor Family I/O for U/Y Platforms [...] Datasheet Volume 1 of 2, page 209 Intel's Document Number: 334658-006, https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/7th-and-8th-gen-core-family-mobile-u-y-processor-lines-i-o-datasheet-vol-1.pdf [3] Functions in arch/x86/kernel/rtc.c apparently were using it. [4] https://bugzilla.redhat.com/show_bug.cgi?id=1936688 Fixes:211e5db19d("rtc: mc146818: Detect and handle broken RTCs") Fixes:ebb22a0594("rtc: mc146818: Dont test for bit 0-5 in Register D") Signed-off-by: Mateusz Jończyk <mat.jonczyk@o2.pl> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Alessandro Zummo <a.zummo@towertech.it> Cc: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Link: https://lore.kernel.org/r/20211210200131.153887-5-mat.jonczyk@o2.pl
130 lines
4.5 KiB
C
130 lines
4.5 KiB
C
/* mc146818rtc.h - register definitions for the Real-Time-Clock / CMOS RAM
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* Copyright Torsten Duwe <duwe@informatik.uni-erlangen.de> 1993
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* derived from Data Sheet, Copyright Motorola 1984 (!).
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* It was written to be part of the Linux operating system.
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*/
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/* permission is hereby granted to copy, modify and redistribute this code
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* in terms of the GNU Library General Public License, Version 2 or later,
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* at your option.
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*/
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#ifndef _MC146818RTC_H
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#define _MC146818RTC_H
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#include <asm/io.h>
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#include <linux/rtc.h> /* get the user-level API */
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#include <asm/mc146818rtc.h> /* register access macros */
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#include <linux/bcd.h>
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#include <linux/delay.h>
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#include <linux/pm-trace.h>
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#ifdef __KERNEL__
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#include <linux/spinlock.h> /* spinlock_t */
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extern spinlock_t rtc_lock; /* serialize CMOS RAM access */
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/* Some RTCs extend the mc146818 register set to support alarms of more
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* than 24 hours in the future; or dates that include a century code.
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* This platform_data structure can pass this information to the driver.
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*
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* Also, some platforms need suspend()/resume() hooks to kick in special
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* handling of wake alarms, e.g. activating ACPI BIOS hooks or setting up
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* a separate wakeup alarm used by some almost-clone chips.
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*/
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struct cmos_rtc_board_info {
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void (*wake_on)(struct device *dev);
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void (*wake_off)(struct device *dev);
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u32 flags;
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#define CMOS_RTC_FLAGS_NOFREQ (1 << 0)
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int address_space;
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u8 rtc_day_alarm; /* zero, or register index */
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u8 rtc_mon_alarm; /* zero, or register index */
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u8 rtc_century; /* zero, or register index */
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};
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#endif
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/**********************************************************************
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* register summary
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**********************************************************************/
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#define RTC_SECONDS 0
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#define RTC_SECONDS_ALARM 1
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#define RTC_MINUTES 2
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#define RTC_MINUTES_ALARM 3
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#define RTC_HOURS 4
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#define RTC_HOURS_ALARM 5
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/* RTC_*_alarm is always true if 2 MSBs are set */
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# define RTC_ALARM_DONT_CARE 0xC0
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#define RTC_DAY_OF_WEEK 6
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#define RTC_DAY_OF_MONTH 7
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#define RTC_MONTH 8
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#define RTC_YEAR 9
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/* control registers - Moto names
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*/
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#define RTC_REG_A 10
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#define RTC_REG_B 11
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#define RTC_REG_C 12
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#define RTC_REG_D 13
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/**********************************************************************
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* register details
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**********************************************************************/
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#define RTC_FREQ_SELECT RTC_REG_A
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/* update-in-progress - set to "1" 244 microsecs before RTC goes off the bus,
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* reset after update (may take 1.984ms @ 32768Hz RefClock) is complete,
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* totalling to a max high interval of 2.228 ms.
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*/
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# define RTC_UIP 0x80
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# define RTC_DIV_CTL 0x70
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/* divider control: refclock values 4.194 / 1.049 MHz / 32.768 kHz */
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# define RTC_REF_CLCK_4MHZ 0x00
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# define RTC_REF_CLCK_1MHZ 0x10
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# define RTC_REF_CLCK_32KHZ 0x20
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/* 2 values for divider stage reset, others for "testing purposes only" */
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# define RTC_DIV_RESET1 0x60
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# define RTC_DIV_RESET2 0x70
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/* Periodic intr. / Square wave rate select. 0=none, 1=32.8kHz,... 15=2Hz */
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# define RTC_RATE_SELECT 0x0F
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/**********************************************************************/
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#define RTC_CONTROL RTC_REG_B
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# define RTC_SET 0x80 /* disable updates for clock setting */
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# define RTC_PIE 0x40 /* periodic interrupt enable */
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# define RTC_AIE 0x20 /* alarm interrupt enable */
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# define RTC_UIE 0x10 /* update-finished interrupt enable */
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# define RTC_SQWE 0x08 /* enable square-wave output */
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# define RTC_DM_BINARY 0x04 /* all time/date values are BCD if clear */
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# define RTC_24H 0x02 /* 24 hour mode - else hours bit 7 means pm */
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# define RTC_DST_EN 0x01 /* auto switch DST - works f. USA only */
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/**********************************************************************/
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#define RTC_INTR_FLAGS RTC_REG_C
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/* caution - cleared by read */
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# define RTC_IRQF 0x80 /* any of the following 3 is active */
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# define RTC_PF 0x40
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# define RTC_AF 0x20
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# define RTC_UF 0x10
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/**********************************************************************/
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#define RTC_VALID RTC_REG_D
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# define RTC_VRT 0x80 /* valid RAM and time */
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/**********************************************************************/
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#ifndef ARCH_RTC_LOCATION /* Override by <asm/mc146818rtc.h>? */
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#define RTC_IO_EXTENT 0x8
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#define RTC_IO_EXTENT_USED 0x2
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#define RTC_IOMAPPED 1 /* Default to I/O mapping. */
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#else
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#define RTC_IO_EXTENT_USED RTC_IO_EXTENT
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#endif /* ARCH_RTC_LOCATION */
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bool mc146818_does_rtc_work(void);
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unsigned int mc146818_get_time(struct rtc_time *time);
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int mc146818_set_time(struct rtc_time *time);
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#endif /* _MC146818RTC_H */
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