mirror of
https://github.com/Fishwaldo/meta-riscv.git
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u-boot: Add patch for OpenSBI fdt driver support
Add 2 patches from mainline U-boot to use with fdt drivers of OpenSBI. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
This commit is contained in:
Yu Chien Peter Lin
Khem Raj
parent
1ae57fa3fd
commit
363d3021de
3 changed files with 321 additions and 0 deletions
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@ -0,0 +1,49 @@
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From bdb238355c37ac175520577fd2355f01db29714b Mon Sep 17 00:00:00 2001
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From: Yu Chien Peter Lin <peterlin@andestech.com>
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Date: Fri, 14 Oct 2022 15:00:18 +0800
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Subject: [PATCH] riscv: andes_plic.c: use modified IPI scheme
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The IPI scheme in OpenSBI has been updated to support 8-core AE350
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platform, the plicsw configuration needs to be modified accordingly.
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Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
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Reviewed-by: Rick Chen <rick@andestech.com>
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The patch was imported from the U-boot git server
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(https://source.denx.de/u-boot/u-boot.git) as of commit id
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bdb238355c37ac175520577fd2355f01db29714b.
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Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
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---
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arch/riscv/lib/andes_plic.c | 7 ++++---
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1 file changed, 4 insertions(+), 3 deletions(-)
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diff --git a/arch/riscv/lib/andes_plic.c b/arch/riscv/lib/andes_plic.c
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index 68514758a8..1eabcacd09 100644
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--- a/arch/riscv/lib/andes_plic.c
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+++ b/arch/riscv/lib/andes_plic.c
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@@ -27,8 +27,8 @@
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/* claim register */
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#define CLAIM_REG(base, hart) ((ulong)(base) + 0x200004 + (hart) * 0x1000)
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-#define ENABLE_HART_IPI (0x80808080)
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-#define SEND_IPI_TO_HART(hart) (0x80 >> (hart))
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+#define ENABLE_HART_IPI (0x01010101)
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+#define SEND_IPI_TO_HART(hart) (0x1 << (hart))
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DECLARE_GLOBAL_DATA_PTR;
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@@ -36,8 +36,9 @@ static int enable_ipi(int hart)
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{
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unsigned int en;
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- en = ENABLE_HART_IPI >> hart;
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+ en = ENABLE_HART_IPI << hart;
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writel(en, (void __iomem *)ENABLE_REG(gd->arch.plic, hart));
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+ writel(en, (void __iomem *)ENABLE_REG(gd->arch.plic + 0x4, hart));
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return 0;
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}
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--
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2.34.1
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@ -0,0 +1,270 @@
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From a5dfa3b8a0f7ad555495bad1386613d2de4ba619 Mon Sep 17 00:00:00 2001
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From: Yu Chien Peter Lin <peterlin@andestech.com>
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Date: Tue, 25 Oct 2022 23:03:50 +0800
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Subject: [PATCH] riscv: Rename Andes PLIC to PLICSW
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As PLICSW is used to trigger the software interrupt, we should rename
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Andes PLIC configuration and file name to reflect the usage. This patch
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also updates PLMT and PLICSW compatible strings to be consistent with
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OpenSBI fdt driver.
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Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
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Reviewed-by: Rick Chen <rick@andestech.com>
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The patch was imported from the U-boot git server
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(https://source.denx.de/u-boot/u-boot.git) as of commit id
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a5dfa3b8a0f7ad555495bad1386613d2de4ba619.
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Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
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---
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arch/riscv/Kconfig | 6 ++---
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arch/riscv/cpu/ax25/Kconfig | 2 +-
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arch/riscv/dts/ae350-u-boot.dtsi | 2 +-
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arch/riscv/dts/ae350_32.dts | 6 ++---
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arch/riscv/dts/ae350_64.dts | 6 ++---
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arch/riscv/include/asm/global_data.h | 4 +--
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arch/riscv/include/asm/syscon.h | 2 +-
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arch/riscv/lib/Makefile | 2 +-
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.../lib/{andes_plic.c => andes_plicsw.c} | 26 +++++++++----------
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drivers/timer/andes_plmt_timer.c | 2 +-
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10 files changed, 29 insertions(+), 29 deletions(-)
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rename arch/riscv/lib/{andes_plic.c => andes_plicsw.c} (76%)
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diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
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index 8f9578171d..4d64e9be3f 100644
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--- a/arch/riscv/Kconfig
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+++ b/arch/riscv/Kconfig
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@@ -199,7 +199,7 @@ config SIFIVE_CACHE
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help
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This enables the operations to configure SiFive cache
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-config ANDES_PLIC
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+config ANDES_PLICSW
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bool
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depends on RISCV_MMODE || SPL_RISCV_MMODE
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select REGMAP
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@@ -207,8 +207,8 @@ config ANDES_PLIC
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select SPL_REGMAP if SPL
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select SPL_SYSCON if SPL
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help
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- The Andes PLIC block holds memory-mapped claim and pending registers
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- associated with software interrupt.
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+ The Andes PLICSW block holds memory-mapped claim and pending
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+ registers associated with software interrupt.
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config SMP
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bool "Symmetric Multi-Processing"
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diff --git a/arch/riscv/cpu/ax25/Kconfig b/arch/riscv/cpu/ax25/Kconfig
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index 941d963ece..4a7295d30c 100644
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--- a/arch/riscv/cpu/ax25/Kconfig
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+++ b/arch/riscv/cpu/ax25/Kconfig
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@@ -4,7 +4,7 @@ config RISCV_NDS
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imply CPU
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imply CPU_RISCV
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imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE)
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- imply ANDES_PLIC if (RISCV_MMODE || SPL_RISCV_MMODE)
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+ imply ANDES_PLICSW if (RISCV_MMODE || SPL_RISCV_MMODE)
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imply ANDES_PLMT_TIMER if (RISCV_MMODE || SPL_RISCV_MMODE)
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imply SPL_CPU
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imply SPL_OPENSBI
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diff --git a/arch/riscv/dts/ae350-u-boot.dtsi b/arch/riscv/dts/ae350-u-boot.dtsi
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index 0d4201cfae..7011f59831 100644
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--- a/arch/riscv/dts/ae350-u-boot.dtsi
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+++ b/arch/riscv/dts/ae350-u-boot.dtsi
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@@ -36,7 +36,7 @@
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soc {
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u-boot,dm-spl;
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- plic1: interrupt-controller@e6400000 {
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+ plicsw: interrupt-controller@e6400000 {
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u-boot,dm-spl;
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};
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diff --git a/arch/riscv/dts/ae350_32.dts b/arch/riscv/dts/ae350_32.dts
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index 083f676333..96ef8bd8dd 100644
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--- a/arch/riscv/dts/ae350_32.dts
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+++ b/arch/riscv/dts/ae350_32.dts
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@@ -146,8 +146,8 @@
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&CPU3_intc 11 &CPU3_intc 9>;
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};
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- plic1: interrupt-controller@e6400000 {
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- compatible = "riscv,plic1";
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+ plicsw: interrupt-controller@e6400000 {
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+ compatible = "andestech,plicsw";
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#interrupt-cells = <1>;
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interrupt-controller;
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reg = <0xe6400000 0x400000>;
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@@ -159,7 +159,7 @@
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};
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plmt0@e6000000 {
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- compatible = "riscv,plmt0";
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+ compatible = "andestech,plmt0";
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interrupts-extended = <&CPU0_intc 7
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&CPU1_intc 7
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&CPU2_intc 7
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diff --git a/arch/riscv/dts/ae350_64.dts b/arch/riscv/dts/ae350_64.dts
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index 74cff9122d..cddbaec98a 100644
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--- a/arch/riscv/dts/ae350_64.dts
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+++ b/arch/riscv/dts/ae350_64.dts
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@@ -146,8 +146,8 @@
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&CPU3_intc 11 &CPU3_intc 9>;
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};
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- plic1: interrupt-controller@e6400000 {
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- compatible = "riscv,plic1";
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+ plicsw: interrupt-controller@e6400000 {
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+ compatible = "andestech,plicsw";
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#interrupt-cells = <2>;
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interrupt-controller;
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reg = <0x0 0xe6400000 0x0 0x400000>;
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@@ -159,7 +159,7 @@
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};
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plmt0@e6000000 {
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- compatible = "riscv,plmt0";
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+ compatible = "andestech,plmt0";
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interrupts-extended = <&CPU0_intc 7
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&CPU1_intc 7
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&CPU2_intc 7
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diff --git a/arch/riscv/include/asm/global_data.h b/arch/riscv/include/asm/global_data.h
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index 858594a191..6fdc86dd8b 100644
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--- a/arch/riscv/include/asm/global_data.h
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+++ b/arch/riscv/include/asm/global_data.h
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@@ -21,8 +21,8 @@ struct arch_global_data {
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#if CONFIG_IS_ENABLED(SIFIVE_CLINT)
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void __iomem *clint; /* clint base address */
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#endif
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-#ifdef CONFIG_ANDES_PLIC
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- void __iomem *plic; /* plic base address */
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+#ifdef CONFIG_ANDES_PLICSW
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+ void __iomem *plicsw; /* plic base address */
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#endif
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#if CONFIG_IS_ENABLED(SMP)
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struct ipi_data ipi[CONFIG_NR_CPUS];
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diff --git a/arch/riscv/include/asm/syscon.h b/arch/riscv/include/asm/syscon.h
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index c3629e4b53..f2b37975f3 100644
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--- a/arch/riscv/include/asm/syscon.h
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+++ b/arch/riscv/include/asm/syscon.h
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@@ -13,7 +13,7 @@
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enum {
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RISCV_NONE,
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RISCV_SYSCON_CLINT, /* Core Local Interruptor (CLINT) */
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- RISCV_SYSCON_PLIC, /* Platform Level Interrupt Controller (PLIC) */
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+ RISCV_SYSCON_PLICSW, /* Andes PLICSW */
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};
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#endif /* _ASM_SYSCON_H */
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diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
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index 06020fcc2a..d6a8ae9728 100644
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--- a/arch/riscv/lib/Makefile
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+++ b/arch/riscv/lib/Makefile
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@@ -13,7 +13,7 @@ obj-y += cache.o
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obj-$(CONFIG_SIFIVE_CACHE) += sifive_cache.o
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ifeq ($(CONFIG_$(SPL_)RISCV_MMODE),y)
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obj-$(CONFIG_$(SPL_)SIFIVE_CLINT) += sifive_clint.o
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-obj-$(CONFIG_ANDES_PLIC) += andes_plic.o
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+obj-$(CONFIG_ANDES_PLICSW) += andes_plicsw.o
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else
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obj-$(CONFIG_SBI) += sbi.o
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obj-$(CONFIG_SBI_IPI) += sbi_ipi.o
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diff --git a/arch/riscv/lib/andes_plic.c b/arch/riscv/lib/andes_plicsw.c
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similarity index 76%
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rename from arch/riscv/lib/andes_plic.c
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rename to arch/riscv/lib/andes_plicsw.c
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index 1eabcacd09..324eb445aa 100644
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--- a/arch/riscv/lib/andes_plic.c
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+++ b/arch/riscv/lib/andes_plicsw.c
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@@ -37,8 +37,8 @@ static int enable_ipi(int hart)
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unsigned int en;
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en = ENABLE_HART_IPI << hart;
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- writel(en, (void __iomem *)ENABLE_REG(gd->arch.plic, hart));
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- writel(en, (void __iomem *)ENABLE_REG(gd->arch.plic + 0x4, hart));
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+ writel(en, (void __iomem *)ENABLE_REG(gd->arch.plicsw, hart));
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+ writel(en, (void __iomem *)ENABLE_REG(gd->arch.plicsw + 0x4, hart));
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return 0;
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}
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@@ -46,14 +46,14 @@ static int enable_ipi(int hart)
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int riscv_init_ipi(void)
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{
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int ret;
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- long *base = syscon_get_first_range(RISCV_SYSCON_PLIC);
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+ long *base = syscon_get_first_range(RISCV_SYSCON_PLICSW);
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ofnode node;
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struct udevice *dev;
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u32 reg;
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if (IS_ERR(base))
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return PTR_ERR(base);
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- gd->arch.plic = base;
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+ gd->arch.plicsw = base;
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ret = uclass_find_first_device(UCLASS_CPU, &dev);
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if (ret)
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@@ -88,7 +88,7 @@ int riscv_send_ipi(int hart)
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{
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unsigned int ipi = (SEND_IPI_TO_HART(hart) << (8 * gd->arch.boot_hart));
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- writel(ipi, (void __iomem *)PENDING_REG(gd->arch.plic,
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+ writel(ipi, (void __iomem *)PENDING_REG(gd->arch.plicsw,
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gd->arch.boot_hart));
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return 0;
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@@ -98,8 +98,8 @@ int riscv_clear_ipi(int hart)
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{
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u32 source_id;
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- source_id = readl((void __iomem *)CLAIM_REG(gd->arch.plic, hart));
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- writel(source_id, (void __iomem *)CLAIM_REG(gd->arch.plic, hart));
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+ source_id = readl((void __iomem *)CLAIM_REG(gd->arch.plicsw, hart));
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+ writel(source_id, (void __iomem *)CLAIM_REG(gd->arch.plicsw, hart));
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return 0;
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}
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@@ -108,21 +108,21 @@ int riscv_get_ipi(int hart, int *pending)
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{
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unsigned int ipi = (SEND_IPI_TO_HART(hart) << (8 * gd->arch.boot_hart));
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- *pending = readl((void __iomem *)PENDING_REG(gd->arch.plic,
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+ *pending = readl((void __iomem *)PENDING_REG(gd->arch.plicsw,
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gd->arch.boot_hart));
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*pending = !!(*pending & ipi);
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return 0;
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}
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-static const struct udevice_id andes_plic_ids[] = {
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- { .compatible = "riscv,plic1", .data = RISCV_SYSCON_PLIC },
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+static const struct udevice_id andes_plicsw_ids[] = {
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+ { .compatible = "andestech,plicsw", .data = RISCV_SYSCON_PLICSW },
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{ }
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};
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-U_BOOT_DRIVER(andes_plic) = {
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- .name = "andes_plic",
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+U_BOOT_DRIVER(andes_plicsw) = {
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+ .name = "andes_plicsw",
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.id = UCLASS_SYSCON,
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- .of_match = andes_plic_ids,
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+ .of_match = andes_plicsw_ids,
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.flags = DM_FLAG_PRE_RELOC,
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};
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diff --git a/drivers/timer/andes_plmt_timer.c b/drivers/timer/andes_plmt_timer.c
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index a3797b22c7..42dd4b6231 100644
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--- a/drivers/timer/andes_plmt_timer.c
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+++ b/drivers/timer/andes_plmt_timer.c
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@@ -56,7 +56,7 @@ static int andes_plmt_probe(struct udevice *dev)
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}
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static const struct udevice_id andes_plmt_ids[] = {
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- { .compatible = "riscv,plmt0" },
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+ { .compatible = "andestech,plmt0" },
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{ }
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};
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--
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2.34.1
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@ -11,6 +11,8 @@ DEPENDS:append = " u-boot-tools-native"
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SRC_URI:append:ae350-ax45mp = " \
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file://0001-mmc-ftsdc010_mci-Support-DTS-of-ftsdc010-driver-for-.patch \
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file://0002-spl-Align-device-tree-blob-address-at-8-byte-boundar.patch \
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file://0003-riscv-andes_plic.c-use-modified-IPI-scheme.patch \
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file://0004-riscv-Rename-Andes-PLIC-to-PLICSW.patch \
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file://mmc-support.cfg \
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file://opensbi-options.cfg \
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file://display-info.cfg \
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Add table
Reference in a new issue