mirror of
https://github.com/Fishwaldo/meta-riscv.git
synced 2025-03-15 19:41:42 +00:00
musl: Add bits/reg.h for riscv32
Applications include sys/reg.h to get wordsize for architecture and such applications would fail to build on rv32/musl if this header is not provided Signed-off-by: Khem Raj <raj.khem@gmail.com>
This commit is contained in:
parent
9d10fd4f37
commit
b022614bc4
2 changed files with 24 additions and 0 deletions
23
recipes-core/musl/musl/0017-Add-bits-reg.h-for-riscv32.patch
Normal file
23
recipes-core/musl/musl/0017-Add-bits-reg.h-for-riscv32.patch
Normal file
|
@ -0,0 +1,23 @@
|
|||
From 707914898f9b5a2738ad188942c3c730889f8f16 Mon Sep 17 00:00:00 2001
|
||||
From: Khem Raj <raj.khem@gmail.com>
|
||||
Date: Thu, 31 Dec 2020 16:07:38 -0800
|
||||
Subject: [PATCH] Add bits/reg.h for riscv32
|
||||
|
||||
Signed-off-by: Khem Raj <raj.khem@gmail.com>
|
||||
---
|
||||
arch/riscv32/bits/reg.h | 3 +++
|
||||
1 file changed, 3 insertions(+)
|
||||
create mode 100644 arch/riscv32/bits/reg.h
|
||||
|
||||
diff --git a/arch/riscv32/bits/reg.h b/arch/riscv32/bits/reg.h
|
||||
new file mode 100644
|
||||
index 00000000..0c7bffca
|
||||
--- /dev/null
|
||||
+++ b/arch/riscv32/bits/reg.h
|
||||
@@ -0,0 +1,3 @@
|
||||
+#undef __WORDSIZE
|
||||
+#define __WORDSIZE 32
|
||||
+/* FIXME */
|
||||
--
|
||||
2.30.0
|
||||
|
|
@ -17,4 +17,5 @@ SRC_URI_append_riscv32 = "\
|
|||
file://0014-riscv32-Add-thread-support.patch \
|
||||
file://0015-Change-definitions-of-F_GETLK-F_SETLK-F_SETLKW.patch \
|
||||
file://0016-riscv32-Wire-new-syscalls.patch \
|
||||
file://0017-Add-bits-reg.h-for-riscv32.patch \
|
||||
"
|
||||
|
|
Loading…
Add table
Reference in a new issue