GitHub-Mirror/opensbi
2
0
Fork 0
mirror of https://github.com/Fishwaldo/opensbi.git synced 2025-03-15 19:31:32 +00:00
Code Issues Projects Releases Packages Wiki Activity Actions

firmware: Reset all registers and flush icache

Browse source 
A warm reset using reset button may put icache and registers
in non-coherent state.

Flush the icache and reset all registers for every hart.

Signed-off-by: Atish Patra <atish.patra@wdc.com>
This commit is contained in:
Atish Patra 2019-03-06 15:18:29 -08:00 • committed by Anup Patel
parent b225583881
commit 007a6b26d9
1 changed files with 4 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

4
firmware/fw_base.S
View file

@ -25,6 +25,8 @@ _start:
csrr a6, CSR_MHARTID
blt zero, a6, _wait_for_boot_hart
li ra, 0
call _reset_regs
/* Zero-out BSS */
la a4, _bss_start
la a5, _bss_end
@ -392,6 +394,8 @@ _trap_handler_all_mode:
.globl _reset_regs
_reset_regs:
/* flush the instruction cache */
fence.i
/* Reset all registers except ra, a0,a1 */
li sp, 0
li gp, 0