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platform: Remove platform/thead
We could use platform/generic instead, and won't use platform/thead/c910 again. Signed-off-by: Guo Ren <guoren@linux.alibaba.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
This commit is contained in:
Guo Ren
Anup Patel
parent
bf3ef53bb7
commit
1db843622a
7 changed files with 0 additions and 259 deletions
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@ -28,9 +28,6 @@ OpenSBI currently supports the following virtual and hardware platforms:
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* **Andes AE350 SoC**: Platform support for the Andes's SoC (AE350). More
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details on this platform can be found in the file *[andes-ae350.md]*.
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* **T-HEAD C910**: Platform support for the T-HEAD C910 Processor. More
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details on this platform can be found in the file *[thead-c910.md]*.
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* **Spike**: Platform support for the Spike emulator. More
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details on this platform can be found in the file *[spike.md]*.
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@ -1,34 +0,0 @@
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T-HEAD C910 Processor
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=====================
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C910 is a 12-stage, 3 issues, 8 executions, out-of-order 64-bit RISC-V CPU which
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supports 16 cores, runs with 2.5GHz, and is capable of running Linux.
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To build platform specific library and firmwares, provide the
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*PLATFORM=thead/c910* parameter to the top level make command.
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Platform Options
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----------------
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The *T-HEAD C910* platform does not have any platform-specific options.
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Building T-HEAD C910 Platform
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-----------------------------
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```
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make PLATFORM=thead/c910
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```
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Booting T-HEAD C910 Platform
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----------------------------
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**No Payload**
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As there's no payload, you may download vmlinux or u-boot to FW_JUMP_ADDR which
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specified in config.mk or compile commands with GDB. And the execution flow will
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turn to vmlinux or u-boot when opensbi ends.
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**Linux Kernel Payload**
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You can also choose to use Linux kernel as payload by enabling FW_PAYLOAD=y
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along with specifying FW_PAYLOAD_OFFSET. The kernel image will be embedded in
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the OPENSBI firmware binary, T-head will directly boot into Linux after OpenSBI.
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@ -1,14 +0,0 @@
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#
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# SPDX-License-Identifier: BSD-2-Clause
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#
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# Compiler flags
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platform-cppflags-y =
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platform-cflags-y =
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platform-asflags-y =
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platform-ldflags-y =
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# Blobs to build
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FW_TEXT_START?=0x0
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FW_JUMP=y
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FW_JUMP_ADDR?=0x00200000
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@ -1,5 +0,0 @@
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#
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# SPDX-License-Identifier: BSD-2-Clause
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#
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platform-objs-y += platform.o
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@ -1,156 +0,0 @@
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/*
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* SPDX-License-Identifier: BSD-2-Clause
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*/
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#include <sbi/riscv_encoding.h>
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#include <sbi/riscv_io.h>
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#include <sbi/sbi_console.h>
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#include <sbi/sbi_const.h>
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#include <sbi/sbi_hart.h>
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#include <sbi/sbi_platform.h>
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#include <sbi_utils/irqchip/plic.h>
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#include <sbi_utils/serial/uart8250.h>
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#include <sbi_utils/sys/clint.h>
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#include "platform.h"
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static struct c910_regs_struct c910_regs;
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static struct clint_data clint = {
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.addr = 0, /* Updated at cold boot time */
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.first_hartid = 0,
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.hart_count = C910_HART_COUNT,
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.has_64bit_mmio = FALSE,
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};
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static int c910_early_init(bool cold_boot)
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{
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if (cold_boot) {
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/* Load from boot core */
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c910_regs.pmpaddr0 = csr_read(CSR_PMPADDR0);
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c910_regs.pmpaddr1 = csr_read(CSR_PMPADDR1);
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c910_regs.pmpaddr2 = csr_read(CSR_PMPADDR2);
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c910_regs.pmpaddr3 = csr_read(CSR_PMPADDR3);
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c910_regs.pmpaddr4 = csr_read(CSR_PMPADDR4);
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c910_regs.pmpaddr5 = csr_read(CSR_PMPADDR5);
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c910_regs.pmpaddr6 = csr_read(CSR_PMPADDR6);
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c910_regs.pmpaddr7 = csr_read(CSR_PMPADDR7);
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c910_regs.pmpcfg0 = csr_read(CSR_PMPCFG0);
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c910_regs.mcor = csr_read(CSR_MCOR);
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c910_regs.mhcr = csr_read(CSR_MHCR);
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c910_regs.mccr2 = csr_read(CSR_MCCR2);
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c910_regs.mhint = csr_read(CSR_MHINT);
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c910_regs.mxstatus = csr_read(CSR_MXSTATUS);
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c910_regs.plic_base_addr = csr_read(CSR_PLIC_BASE);
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c910_regs.clint_base_addr =
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c910_regs.plic_base_addr + C910_PLIC_CLINT_OFFSET;
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} else {
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/* Store to other core */
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csr_write(CSR_PMPADDR0, c910_regs.pmpaddr0);
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csr_write(CSR_PMPADDR1, c910_regs.pmpaddr1);
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csr_write(CSR_PMPADDR2, c910_regs.pmpaddr2);
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csr_write(CSR_PMPADDR3, c910_regs.pmpaddr3);
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csr_write(CSR_PMPADDR4, c910_regs.pmpaddr4);
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csr_write(CSR_PMPADDR5, c910_regs.pmpaddr5);
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csr_write(CSR_PMPADDR6, c910_regs.pmpaddr6);
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csr_write(CSR_PMPADDR7, c910_regs.pmpaddr7);
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csr_write(CSR_PMPCFG0, c910_regs.pmpcfg0);
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csr_write(CSR_MCOR, c910_regs.mcor);
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csr_write(CSR_MHCR, c910_regs.mhcr);
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csr_write(CSR_MHINT, c910_regs.mhint);
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csr_write(CSR_MXSTATUS, c910_regs.mxstatus);
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}
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return 0;
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}
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static int c910_final_init(bool cold_boot)
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{
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return 0;
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}
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static int c910_irqchip_init(bool cold_boot)
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{
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/* Delegate plic enable into S-mode */
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writel(C910_PLIC_DELEG_ENABLE,
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(void *)c910_regs.plic_base_addr + C910_PLIC_DELEG_OFFSET);
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return 0;
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}
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static int c910_ipi_init(bool cold_boot)
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{
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int rc;
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if (cold_boot) {
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clint.addr = c910_regs.clint_base_addr;
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rc = clint_cold_ipi_init(&clint);
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if (rc)
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return rc;
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}
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return clint_warm_ipi_init();
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}
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static int c910_timer_init(bool cold_boot)
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{
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int ret;
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if (cold_boot) {
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clint.addr = c910_regs.clint_base_addr;
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ret = clint_cold_timer_init(&clint, NULL);
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if (ret)
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return ret;
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}
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return clint_warm_timer_init();
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}
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static int c910_system_reset_check(u32 type, u32 reason)
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{
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return 1;
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}
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static void c910_system_reset(u32 type, u32 reason)
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{
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asm volatile ("ebreak");
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}
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int c910_hart_start(u32 hartid, ulong saddr)
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{
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csr_write(CSR_MRVBR, saddr);
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csr_write(CSR_MRMR, csr_read(CSR_MRMR) | (1 << hartid));
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return 0;
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}
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const struct sbi_platform_operations platform_ops = {
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.early_init = c910_early_init,
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.final_init = c910_final_init,
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.irqchip_init = c910_irqchip_init,
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.ipi_init = c910_ipi_init,
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.ipi_send = clint_ipi_send,
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.ipi_clear = clint_ipi_clear,
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.timer_init = c910_timer_init,
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.timer_event_start = clint_timer_event_start,
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.system_reset_check = c910_system_reset_check,
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.system_reset = c910_system_reset,
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.hart_start = c910_hart_start,
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};
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const struct sbi_platform platform = {
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.opensbi_version = OPENSBI_VERSION,
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.platform_version = SBI_PLATFORM_VERSION(0x0, 0x01),
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.name = "T-HEAD Xuantie c910",
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.features = SBI_THEAD_FEATURES,
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.hart_count = C910_HART_COUNT,
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.hart_stack_size = SBI_PLATFORM_DEFAULT_HART_STACK_SIZE,
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.platform_ops_addr = (unsigned long)&platform_ops
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};
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@ -1,46 +0,0 @@
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/*
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* SPDX-License-Identifier: BSD-2-Clause
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*/
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#ifndef _C910_PLATFORM_H_
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#define _C910_PLATFORM_H_
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#define C910_HART_COUNT 16
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#define SBI_THEAD_FEATURES \
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(SBI_PLATFORM_HAS_MFAULTS_DELEGATION | \
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SBI_PLATFORM_HAS_HART_SECONDARY_BOOT)
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#define CSR_MCOR 0x7c2
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#define CSR_MHCR 0x7c1
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#define CSR_MCCR2 0x7c3
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#define CSR_MHINT 0x7c5
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#define CSR_MXSTATUS 0x7c0
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#define CSR_PLIC_BASE 0xfc1
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#define CSR_MRMR 0x7c6
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#define CSR_MRVBR 0x7c7
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#define C910_PLIC_CLINT_OFFSET 0x04000000 /* 64M */
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#define C910_PLIC_DELEG_OFFSET 0x001ffffc
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#define C910_PLIC_DELEG_ENABLE 0x1
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struct c910_regs_struct {
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u64 pmpaddr0;
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u64 pmpaddr1;
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u64 pmpaddr2;
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u64 pmpaddr3;
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u64 pmpaddr4;
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u64 pmpaddr5;
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u64 pmpaddr6;
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u64 pmpaddr7;
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u64 pmpcfg0;
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u64 mcor;
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u64 mhcr;
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u64 mccr2;
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u64 mhint;
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u64 mxstatus;
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u64 plic_base_addr;
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u64 clint_base_addr;
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};
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#endif /* _C910_PLATFORM_H_ */
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@ -106,7 +106,6 @@ build_opensbi() {
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BUILD_PLATFORM_SUBDIR+=("fpga/ariane")
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BUILD_PLATFORM_SUBDIR+=("fpga/openpiton")
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BUILD_PLATFORM_SUBDIR+=("andes/ae350")
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BUILD_PLATFORM_SUBDIR+=("thead/c910")
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BUILD_PLATFORM_SUBDIR+=("generic")
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;;
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*)
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