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firmware: fw_base: Optimize trap handler for RV32 systems
On RV32 systems, we have two CSRs for M-mode status (MSTATUS and MSTATUSH) when H-extension is implemented. This means we have to save/restore MSTATUSH for RV32 systems only when H-extension is implemented. The current _trap_handler() has extra instructions (roughly 10) for conditional save/restore of MSTATUSH CSR. These extra instructions in RV32 _trap_handler() can be avoided if we create separate low-level trap handler for RV32 systems having H-extension. This patch optimizes low-level trap handler for RV32 systems accordingly. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
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1 changed files with 68 additions and 19 deletions
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@ -413,6 +413,14 @@ _start_warm:
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/* Setup trap handler */
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la a4, _trap_handler
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#if __riscv_xlen == 32
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csrr a5, CSR_MISA
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srli a5, a5, ('H' - 'A')
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andi a5, a5, 0x1
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beq a5, zero, _skip_trap_handler_rv32_hyp
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la a4, _trap_handler_rv32_hyp
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_skip_trap_handler_rv32_hyp:
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#endif
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csrw CSR_MTVEC, a4
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/* Initialize SBI runtime */
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@ -476,10 +484,7 @@ fw_platform_init:
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add a0, a1, zero
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ret
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.section .entry, "ax", %progbits
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.align 3
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.globl _trap_handler
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_trap_handler:
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.macro TRAP_SAVE_AND_SETUP_SP_T0
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/* Swap TP and MSCRATCH */
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csrrw tp, CSR_MSCRATCH, tp
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@ -519,23 +524,23 @@ _trap_handler:
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/* Swap TP and MSCRATCH */
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csrrw tp, CSR_MSCRATCH, tp
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.endm
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.macro TRAP_SAVE_MEPC_MSTATUS have_mstatush
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/* Save MEPC and MSTATUS CSRs */
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csrr t0, CSR_MEPC
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REG_S t0, SBI_TRAP_REGS_OFFSET(mepc)(sp)
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csrr t0, CSR_MSTATUS
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REG_S t0, SBI_TRAP_REGS_OFFSET(mstatus)(sp)
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REG_S zero, SBI_TRAP_REGS_OFFSET(mstatusH)(sp)
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#if __riscv_xlen == 32
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csrr t0, CSR_MISA
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srli t0, t0, ('H' - 'A')
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andi t0, t0, 0x1
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beq t0, zero, _skip_mstatush_save
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.if \have_mstatush
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csrr t0, CSR_MSTATUSH
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REG_S t0, SBI_TRAP_REGS_OFFSET(mstatusH)(sp)
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_skip_mstatush_save:
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#endif
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.else
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REG_S zero, SBI_TRAP_REGS_OFFSET(mstatusH)(sp)
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.endif
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.endm
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.macro TRAP_SAVE_GENERAL_REGS_EXCEPT_SP_T0
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/* Save all general regisers except SP and T0 */
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REG_S zero, SBI_TRAP_REGS_OFFSET(zero)(sp)
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REG_S ra, SBI_TRAP_REGS_OFFSET(ra)(sp)
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@ -567,11 +572,15 @@ _skip_mstatush_save:
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REG_S t4, SBI_TRAP_REGS_OFFSET(t4)(sp)
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REG_S t5, SBI_TRAP_REGS_OFFSET(t5)(sp)
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REG_S t6, SBI_TRAP_REGS_OFFSET(t6)(sp)
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.endm
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.macro TRAP_CALL_C_ROUTINE
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/* Call C routine */
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add a0, sp, zero
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call sbi_trap_handler
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.endm
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.macro TRAP_RESTORE_GENERAL_REGS_EXCEPT_SP_T0
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/* Restore all general regisers except SP and T0 */
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REG_L ra, SBI_TRAP_REGS_OFFSET(ra)(sp)
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REG_L gp, SBI_TRAP_REGS_OFFSET(gp)(sp)
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@ -602,30 +611,70 @@ _skip_mstatush_save:
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REG_L t4, SBI_TRAP_REGS_OFFSET(t4)(sp)
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REG_L t5, SBI_TRAP_REGS_OFFSET(t5)(sp)
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REG_L t6, SBI_TRAP_REGS_OFFSET(t6)(sp)
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.endm
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.macro TRAP_RESTORE_MEPC_MSTATUS have_mstatush
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/* Restore MEPC and MSTATUS CSRs */
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REG_L t0, SBI_TRAP_REGS_OFFSET(mepc)(sp)
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csrw CSR_MEPC, t0
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REG_L t0, SBI_TRAP_REGS_OFFSET(mstatus)(sp)
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csrw CSR_MSTATUS, t0
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#if __riscv_xlen == 32
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csrr t0, CSR_MISA
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srli t0, t0, ('H' - 'A')
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andi t0, t0, 0x1
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beq t0, zero, _skip_mstatush_restore
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.if \have_mstatush
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REG_L t0, SBI_TRAP_REGS_OFFSET(mstatusH)(sp)
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csrw CSR_MSTATUSH, t0
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_skip_mstatush_restore:
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#endif
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.endif
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.endm
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.macro TRAP_RESTORE_SP_T0
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/* Restore T0 */
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REG_L t0, SBI_TRAP_REGS_OFFSET(t0)(sp)
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/* Restore SP */
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REG_L sp, SBI_TRAP_REGS_OFFSET(sp)(sp)
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.endm
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.section .entry, "ax", %progbits
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.align 3
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.globl _trap_handler
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_trap_handler:
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TRAP_SAVE_AND_SETUP_SP_T0
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TRAP_SAVE_MEPC_MSTATUS 0
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TRAP_SAVE_GENERAL_REGS_EXCEPT_SP_T0
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TRAP_CALL_C_ROUTINE
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TRAP_RESTORE_GENERAL_REGS_EXCEPT_SP_T0
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TRAP_RESTORE_MEPC_MSTATUS 0
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TRAP_RESTORE_SP_T0
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mret
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#if __riscv_xlen == 32
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.section .entry, "ax", %progbits
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.align 3
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.globl _trap_handler_rv32_hyp
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_trap_handler_rv32_hyp:
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TRAP_SAVE_AND_SETUP_SP_T0
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TRAP_SAVE_MEPC_MSTATUS 1
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TRAP_SAVE_GENERAL_REGS_EXCEPT_SP_T0
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TRAP_CALL_C_ROUTINE
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TRAP_RESTORE_GENERAL_REGS_EXCEPT_SP_T0
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TRAP_RESTORE_MEPC_MSTATUS 1
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TRAP_RESTORE_SP_T0
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mret
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#endif
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.section .entry, "ax", %progbits
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.align 3
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.globl _reset_regs
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