GitHub-Mirror/opensbi
2
0
Fork 0
mirror of https://github.com/Fishwaldo/opensbi.git synced 2025-03-15 19:31:32 +00:00
Code Issues Projects Releases Packages Wiki Activity Actions

firmware: Reset all the general purpose registers to zero.

Browse source 
A warm reset by pressing the reset button may not initialize all the
registers to zero. Do it for every hart during warm boot.

Signed-off-by: Atish Patra <atish.patra@wdc.com>
This commit is contained in:
Atish Patra 2019-03-04 14:08:17 -08:00 • committed by Anup Patel
parent d4dd2b37f3
commit 27fae182dc
1 changed files with 41 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

41
firmware/fw_base.S
View file

@ -120,6 +120,9 @@ _wait_for_boot_hart:
beqz a5, _wait_for_boot_hart
_start_warm:
li ra, 0
call _reset_regs
/* Disable and clear all interrupts */
csrw CSR_MIE, zero
csrw CSR_MIP, zero
@ -380,3 +383,41 @@ _trap_handler_all_mode:
REG_L sp, SBI_TRAP_REGS_OFFSET(sp)(sp)
mret
.align 3
.section .entry, "ax", %progbits
.globl _reset_regs
_reset_regs:
/* Reset all registers except ra, a0,a1 */
li sp, 0
li gp, 0
li tp, 0
li t0, 0
li t1, 0
li t2, 0
li s0, 0
li s1, 0
li a2, 0
li a3, 0
li a4, 0
li a5, 0
li a6, 0
li a7, 0
li s2, 0
li s3, 0
li s4, 0
li s5, 0
li s6, 0
li s7, 0
li s8, 0
li s9, 0
li s10, 0
li s11, 0
li t3, 0
li t4, 0
li t5, 0
li t6, 0
csrw CSR_MSCRATCH, 0
ret