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lib: sbi_hart: Enable hcontext and scontext
According to the description in "riscv-state-enable[0]", to access
h/scontext in S-Mode, we need to enable the 57th bit.
If it is not enabled, an "illegal instruction" error will occur.
Link: a28bfae443/content.adoc
[0]
Signed-off-by: Nylon Chen <nylon.chen@sifive.com>
Reviewed-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
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2 changed files with 3 additions and 0 deletions
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@ -736,6 +736,8 @@
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#define SMSTATEEN0_CS (_ULL(1) << SMSTATEEN0_CS_SHIFT)
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#define SMSTATEEN0_FCSR_SHIFT 1
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#define SMSTATEEN0_FCSR (_ULL(1) << SMSTATEEN0_FCSR_SHIFT)
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#define SMSTATEEN0_CONTEXT_SHIFT 57
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#define SMSTATEEN0_CONTEXT (_ULL(1) << SMSTATEEN0_CONTEXT_SHIFT)
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#define SMSTATEEN0_IMSIC_SHIFT 58
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#define SMSTATEEN0_IMSIC (_ULL(1) << SMSTATEEN0_IMSIC_SHIFT)
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#define SMSTATEEN0_AIA_SHIFT 59
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@ -90,6 +90,7 @@ static void mstatus_init(struct sbi_scratch *scratch)
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mstateen_val |= ((uint64_t)csr_read(CSR_MSTATEEN0H)) << 32;
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#endif
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mstateen_val |= SMSTATEEN_STATEN;
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mstateen_val |= SMSTATEEN0_CONTEXT;
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mstateen_val |= SMSTATEEN0_HSENVCFG;
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if (sbi_hart_has_extension(scratch, SBI_HART_EXT_SMAIA))
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