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platform: Add Andes AE350 initial support
This commit provides basic support for the AE350 platform. Signed-off-by: Zong Li <zongbox@gmail.com> Signed-off-by: Nylon Chen <nylon7@andestech.com>
This commit is contained in:
Nylon Chen
Anup Patel
parent
a2a7763ac7
commit
3cbb419def
10 changed files with 650 additions and 0 deletions
28
docs/platform/andes-ae350.md
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28
docs/platform/andes-ae350.md
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@ -0,0 +1,28 @@
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Andes AE350 SoC Platform
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========================
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The AE350 AXI/AHB-based platform N25(F)/NX25(F)/D25F/A25/AX25 CPU with
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level-one memories,interrupt controller, debug module, AXI and AHB Bus
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Matrix Controller, AXI-to-AHB Bridge and a collection of fundamentalAHB/APB
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bus IP components pre-integrated together as a system design.The high-quality
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and configurable AHB/APB IPs suites a majority embedded systems,
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and the verified platform serves as a starting point to jump start SoC designs.
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To build platform specific library and firmwares, provide the *PLATFORM=andes/ae350* parameter to the top level make command.
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Platform Options
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----------------
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The Andes AE350 platform does not have any platform-specific options.
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Building Andes AE350 Platform
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-----------------------------
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To use Linux v5.2 should be used to build Andes AE350 OpenSBI binaries by using the compile time option FW_PAYLOAD_FDT_PATH.
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AE350's dts is included in https://github.com/andestech/linux/tree/ast-v3_2_0-release-public
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**Linux Kernel Payload**
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```
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make PLATFORM=andes/ae350 FW_PAYLOAD_PATH=<linux_build_directory>/arch/riscv/boot/Image FW_PAYLOAD_FDT_PATH=<ae350.dtb path>
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```
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@ -24,6 +24,8 @@ OpenSBI currently supports the following virtual and hardware platforms:
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* **Ariane FPGA SoC**: Platform support for the Ariane FPGA SoC used on
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Genesys 2 board.
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* **Andes AE350 SoC**: Platform support for the Andes's SoC (AE350).
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The code for these supported platforms can be used as example to implement
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support for other platforms. The *platform/template* directory also provides
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template files for implementing support for a new platform. The *object.mk*,
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@ -34,3 +36,4 @@ facilitate the implementation.
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[qemu_sifive_u.md]: qemu_sifive_u.md
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[sifive_fu540.md]: sifive_fu540.md
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[ariane-fpga.md]: ariane-fpga.md
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[andes_ae350.md]: andes-ae350.md
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36
platform/andes/ae350/config.mk
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36
platform/andes/ae350/config.mk
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@ -0,0 +1,36 @@
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#
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# SPDX-License-Identifier: BSD-2-Clause
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#
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# Copyright (c) 2019 Andes Technology Corporation
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#
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# Authors:
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# Zong Li <zong@andestech.com>
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# Nylon Chen <nylon7@andestech.com>
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# Compiler flags
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platform-cppflags-y =
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platform-cflags-y =
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platform-asflags-y =
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platform-ldflags-y =
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# Blobs to build
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FW_TEXT_START=0x00000000
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FW_DYNAMIC=y
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FW_JUMP=y
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ifeq ($(PLATFORM_RISCV_XLEN), 32)
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FW_JUMP_ADDR=0x400000
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else
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FW_JUMP_ADDR=0x200000
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endif
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FW_JUMP_FDT_ADDR=0x2000000
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FW_PAYLOAD=y
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ifeq ($(PLATFORM_RISCV_XLEN), 32)
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FW_PAYLOAD_OFFSET=0x400000
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else
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FW_PAYLOAD_OFFSET=0x200000
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endif
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FW_PAYLOAD_FDT_ADDR=0x2000000
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11
platform/andes/ae350/objects.mk
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11
platform/andes/ae350/objects.mk
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@ -0,0 +1,11 @@
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#
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# SPDX-License-Identifier: BSD-2-Clause
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#
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# Copyright (c) 2019 Andes Technology Corporation
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#
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# Authors:
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# Zong Li <zong@andestech.com>
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# Nylon Chen <nylon7@andestech.com>
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#
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platform-objs-y += plicsw.o plmt.o platform.o
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194
platform/andes/ae350/platform.c
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194
platform/andes/ae350/platform.c
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@ -0,0 +1,194 @@
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/*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2019 Andes Technology Corporation
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*
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* Authors:
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* Zong Li <zong@andestech.com>
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* Nylon Chen <nylon7@andestech.com>
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*/
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#include <sbi/riscv_encoding.h>
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#include <sbi/sbi_const.h>
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#include <sbi/sbi_hart.h>
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#include <sbi/sbi_platform.h>
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#include <sbi/sbi_console.h>
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#include <sbi_utils/serial/uart8250.h>
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#include <sbi_utils/irqchip/plic.h>
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#include "platform.h"
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#include "plmt.h"
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#include "plicsw.h"
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/* Platform final initialization. */
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static int ae350_final_init(bool cold_boot)
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{
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void *fdt;
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/* enable L1 cache */
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uintptr_t mcache_ctl_val = csr_read(CSR_MCACHECTL);
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if (!(mcache_ctl_val & V5_MCACHE_CTL_IC_EN))
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mcache_ctl_val |= V5_MCACHE_CTL_IC_EN;
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if (!(mcache_ctl_val & V5_MCACHE_CTL_DC_EN))
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mcache_ctl_val |= V5_MCACHE_CTL_DC_EN;
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if (!(mcache_ctl_val & V5_MCACHE_CTL_CCTL_SUEN))
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mcache_ctl_val |= V5_MCACHE_CTL_CCTL_SUEN;
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csr_write(CSR_MCACHECTL, mcache_ctl_val);
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/* enable L2 cache */
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uint32_t *l2c_ctl_base = (void *)AE350_L2C_ADDR + V5_L2C_CTL_OFFSET;
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uint32_t l2c_ctl_val = *l2c_ctl_base;
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if (!(l2c_ctl_val & V5_L2C_CTL_ENABLE_MASK))
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l2c_ctl_val |= V5_L2C_CTL_ENABLE_MASK;
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*l2c_ctl_base = l2c_ctl_val;
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if (!cold_boot)
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return 0;
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fdt = sbi_scratch_thishart_arg1_ptr();
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plic_fdt_fixup(fdt, "riscv,plic0");
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return 0;
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}
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/* Get number of PMP regions for given HART. */
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static u32 ae350_pmp_region_count(u32 hartid)
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{
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return 1;
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}
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/*
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* Get PMP regions details (namely: protection, base address, and size) for
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* a given HART.
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*/
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static int ae350_pmp_region_info(u32 hartid, u32 index, ulong *prot,
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ulong *addr, ulong *log2size)
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{
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int ret = 0;
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switch (index) {
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case 0:
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*prot = PMP_R | PMP_W | PMP_X;
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*addr = 0;
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*log2size = __riscv_xlen;
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break;
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default:
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ret = -1;
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break;
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};
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return ret;
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}
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/* Initialize the platform console. */
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static int ae350_console_init(void)
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{
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return uart8250_init(AE350_UART_ADDR,
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AE350_UART_FREQUENCY,
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AE350_UART_BAUDRATE,
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AE350_UART_REG_SHIFT,
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AE350_UART_REG_WIDTH);
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}
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/* Initialize the platform interrupt controller for current HART. */
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static int ae350_irqchip_init(bool cold_boot)
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{
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u32 hartid = sbi_current_hartid();
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int ret;
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if (cold_boot) {
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ret = plic_cold_irqchip_init(AE350_PLIC_ADDR,
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AE350_PLIC_NUM_SOURCES,
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AE350_HART_COUNT);
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if (ret)
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return ret;
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}
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return plic_warm_irqchip_init(hartid, 2 * hartid, 2 * hartid + 1);
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}
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/* Initialize IPI for current HART. */
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static int ae350_ipi_init(bool cold_boot)
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{
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int ret;
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if (cold_boot) {
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ret = plicsw_cold_ipi_init(AE350_PLICSW_ADDR,
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AE350_HART_COUNT);
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if (ret)
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return ret;
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}
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return plicsw_warm_ipi_init();
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}
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/* Initialize platform timer for current HART. */
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static int ae350_timer_init(bool cold_boot)
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{
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int ret;
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if (cold_boot) {
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ret = plmt_cold_timer_init(AE350_PLMT_ADDR,
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AE350_HART_COUNT);
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if (ret)
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return ret;
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}
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return plmt_warm_timer_init();
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}
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/* Reboot the platform. */
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static int ae350_system_reboot(u32 type)
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{
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/* For now nothing to do. */
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sbi_printf("System reboot\n");
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return 0;
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}
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/* Shutdown or poweroff the platform. */
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static int ae350_system_shutdown(u32 type)
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{
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/* For now nothing to do. */
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sbi_printf("System shutdown\n");
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return 0;
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}
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/* Platform descriptor. */
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const struct sbi_platform_operations platform_ops = {
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.final_init = ae350_final_init,
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.pmp_region_count = ae350_pmp_region_count,
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.pmp_region_info = ae350_pmp_region_info,
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.console_init = ae350_console_init,
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.console_putc = uart8250_putc,
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.console_getc = uart8250_getc,
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.irqchip_init = ae350_irqchip_init,
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.ipi_init = ae350_ipi_init,
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.ipi_send = plicsw_ipi_send,
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.ipi_clear = plicsw_ipi_clear,
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.timer_init = ae350_timer_init,
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.timer_value = plmt_timer_value,
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.timer_event_start = plmt_timer_event_start,
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.timer_event_stop = plmt_timer_event_stop,
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.system_reboot = ae350_system_reboot,
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.system_shutdown = ae350_system_shutdown
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};
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const struct sbi_platform platform = {
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.opensbi_version = OPENSBI_VERSION,
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.platform_version = SBI_PLATFORM_VERSION(0x0, 0x01),
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.name = "Andes AE350",
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.features = SBI_PLATFORM_DEFAULT_FEATURES,
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.hart_count = AE350_HART_COUNT,
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.hart_stack_size = AE350_HART_STACK_SIZE,
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.disabled_hart_mask = 0,
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.platform_ops_addr = (unsigned long)&platform_ops
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};
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67
platform/andes/ae350/platform.h
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67
platform/andes/ae350/platform.h
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@ -0,0 +1,67 @@
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/*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2019 Andes Technology Corporation
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*
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* Authors:
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* Zong Li <zong@andestech.com>
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* Nylon Chen <nylon7@andestech.com>
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*/
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#ifndef _AE350_PLATFORM_H_
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#define _AE350_PLATFORM_H_
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#define AE350_HART_COUNT 4
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#define AE350_HART_STACK_SIZE 8192
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#define AE350_PLIC_ADDR 0xe4000000
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#define AE350_PLIC_NUM_SOURCES 71
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#define AE350_PLICSW_ADDR 0xe6400000
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#define AE350_PLMT_ADDR 0xe6000000
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#define AE350_L2C_ADDR 0xe0500000
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#define AE350_UART_ADDR_OFFSET 0x20
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#define AE350_UART_ADDR (0xf0300000 + AE350_UART_ADDR_OFFSET)
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#define AE350_UART_FREQUENCY 19660800
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#define AE350_UART_BAUDRATE 38400
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#define AE350_UART_REG_SHIFT 2
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#define AE350_UART_REG_WIDTH 0
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/* nds mcache_ctl register*/
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#define CSR_MCACHECTL 0x7ca
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#define V5_MCACHE_CTL_IC_EN_OFFSET 0
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#define V5_MCACHE_CTL_DC_EN_OFFSET 1
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#define V5_MCACHE_CTL_IC_ECCEN_OFFSET 2
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#define V5_MCACHE_CTL_DC_ECCEN_OFFSET 4
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#define V5_MCACHE_CTL_IC_RWECC_OFFSET 6
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#define V5_MCACHE_CTL_DC_RWECC_OFFSET 7
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#define V5_MCACHE_CTL_CCTL_SUEN_OFFSET 8
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#define V5_MCACHE_CTL_IC_EN (1UL << V5_MCACHE_CTL_IC_EN_OFFSET)
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#define V5_MCACHE_CTL_DC_EN (1UL << V5_MCACHE_CTL_DC_EN_OFFSET)
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#define V5_MCACHE_CTL_IC_RWECC (1UL << V5_MCACHE_CTL_IC_RWECC_OFFSET)
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#define V5_MCACHE_CTL_DC_RWECC (1UL << V5_MCACHE_CTL_DC_RWECC_OFFSET)
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#define V5_MCACHE_CTL_CCTL_SUEN (1UL << V5_MCACHE_CTL_CCTL_SUEN_OFFSET)
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#define V5_L2C_CTL_OFFSET 0x8
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#define V5_L2C_CTL_ENABLE_OFFSET 0
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#define V5_L2C_CTL_IPFDPT_OFFSET 3
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#define V5_L2C_CTL_DPFDPT_OFFSET 5
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#define V5_L2C_CTL_TRAMOCTL_OFFSET 8
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#define V5_L2C_CTL_TRAMICTL_OFFSET 10
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#define V5_L2C_CTL_DRAMOCTL_OFFSET 11
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#define V5_L2C_CTL_DRAMICTL_OFFSET 13
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#define V5_L2C_CTL_ENABLE_MASK (1UL << V5_L2C_CTL_ENABLE_OFFSET)
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#define V5_L2C_CTL_IPFDPT_MASK (3UL << V5_L2C_CTL_IPFDPT_OFFSET)
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#define V5_L2C_CTL_DPFDPT_MASK (3UL << V5_L2C_CTL_DPFDPT_OFFSET)
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#define V5_L2C_CTL_TRAMOCTL_MASK (3UL << V5_L2C_CTL_TRAMOCTL_OFFSET)
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#define V5_L2C_CTL_TRAMICTL_MASK (1UL << V5_L2C_CTL_TRAMICTL_OFFSET)
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#define V5_L2C_CTL_DRAMOCTL_MASK (3UL << V5_L2C_CTL_DRAMOCTL_OFFSET)
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#define V5_L2C_CTL_DRAMICTL_MASK (1UL << V5_L2C_CTL_DRAMICTL_OFFSET)
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#endif /* _AE350_PLATFORM_H_ */
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145
platform/andes/ae350/plicsw.c
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145
platform/andes/ae350/plicsw.c
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@ -0,0 +1,145 @@
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/*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2019 Andes Technology Corporation
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*
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* Authors:
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* Zong Li <zong@andestech.com>
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* Nylon Chen <nylon7@andestech.com>
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*/
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#include <sbi/sbi_types.h>
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#include <sbi/sbi_hart.h>
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#include <sbi/riscv_io.h>
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#include "plicsw.h"
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#include "platform.h"
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static u32 plicsw_ipi_hart_count;
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static struct plicsw plicsw_dev[AE350_HART_COUNT];
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static inline void plicsw_claim(void)
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{
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u32 source_hart = sbi_current_hartid();
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plicsw_dev[source_hart].source_id =
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readl(plicsw_dev[source_hart].plicsw_claim);
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}
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static inline void plicsw_complete(void)
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{
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u32 source_hart = sbi_current_hartid();
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u32 source = plicsw_dev[source_hart].source_id;
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writel(source, plicsw_dev[source_hart].plicsw_claim);
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}
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static inline u32 plicsw_get_pending(u32 source_hart, u32 target_hart)
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{
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return readl(plicsw_dev[source_hart].plicsw_pending)
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& (PLICSW_HART_MASK >> target_hart);
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}
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static inline void plic_sw_pending(u32 target_hart)
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{
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/*
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* The pending array registers are w1s type.
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* IPI pending array mapping as following:
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*
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* Pending array start address: base + 0x1000
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* -------------------------------------
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* | hart 3 | hart 2 | hart 1 | hart 0 |
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* -------------------------------------
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* Each hart X can send IPI to another hart by setting the
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* corresponding bit in hart X own region(see the below).
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*
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* In each hart region:
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* -----------------------------------------------
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* | bit 7 | bit 6 | bit 5 | bit 4 | ... | bit 0 |
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* -----------------------------------------------
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* The bit 7 is used to send IPI to hart 0
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* The bit 6 is used to send IPI to hart 1
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* The bit 5 is used to send IPI to hart 2
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* The bit 4 is used to send IPI to hart 3
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*/
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u32 source_hart = sbi_current_hartid();
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u32 target_offset = (PLICSW_PENDING_PER_HART - 1) - target_hart;
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u32 per_hart_offset = PLICSW_PENDING_PER_HART * source_hart;
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u32 val = 1 << target_offset << per_hart_offset;
|
||||
|
||||
writel(val, plicsw_dev[source_hart].plicsw_pending);
|
||||
}
|
||||
|
||||
void plicsw_ipi_send(u32 target_hart)
|
||||
{
|
||||
if (plicsw_ipi_hart_count <= target_hart)
|
||||
return;
|
||||
|
||||
/* Set PLICSW IPI */
|
||||
plic_sw_pending(target_hart);
|
||||
}
|
||||
|
||||
void plicsw_ipi_clear(u32 target_hart)
|
||||
{
|
||||
if (plicsw_ipi_hart_count <= target_hart)
|
||||
return;
|
||||
|
||||
/* Clear CLINT IPI */
|
||||
plicsw_claim();
|
||||
plicsw_complete();
|
||||
}
|
||||
|
||||
int plicsw_warm_ipi_init(void)
|
||||
{
|
||||
u32 hartid = sbi_current_hartid();
|
||||
|
||||
if (!plicsw_dev[hartid].plicsw_pending
|
||||
&& !plicsw_dev[hartid].plicsw_enable
|
||||
&& !plicsw_dev[hartid].plicsw_claim)
|
||||
return -1;
|
||||
|
||||
/* Clear PLICSW IPI */
|
||||
plicsw_ipi_clear(hartid);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int plicsw_cold_ipi_init(unsigned long base, u32 hart_count)
|
||||
{
|
||||
/* Setup source priority */
|
||||
uint32_t *priority = (void *)base + PLICSW_PRIORITY_BASE;
|
||||
|
||||
for (int i = 0; i < AE350_HART_COUNT*PLICSW_PENDING_PER_HART; i++)
|
||||
writel(1, &priority[i]);
|
||||
|
||||
/* Setup target enable.*/
|
||||
uint32_t enable_mask = PLICSW_HART_MASK;
|
||||
|
||||
for (int i = 0; i < AE350_HART_COUNT; i++) {
|
||||
uint32_t *enable = (void *)base + PLICSW_ENABLE_BASE
|
||||
+ PLICSW_ENABLE_PER_HART * i;
|
||||
writel(enable_mask, &enable[0]);
|
||||
enable_mask >>= 1;
|
||||
}
|
||||
|
||||
/* Figure-out PLICSW IPI register address */
|
||||
plicsw_ipi_hart_count = hart_count;
|
||||
|
||||
for (u32 hartid = 0; hartid < AE350_HART_COUNT; hartid++) {
|
||||
plicsw_dev[hartid].source_id = 0;
|
||||
plicsw_dev[hartid].plicsw_pending =
|
||||
(void *)base
|
||||
+ PLICSW_PENDING_BASE
|
||||
+ ((hartid / 4) * 4);
|
||||
plicsw_dev[hartid].plicsw_enable =
|
||||
(void *)base
|
||||
+ PLICSW_ENABLE_BASE
|
||||
+ PLICSW_ENABLE_PER_HART * hartid;
|
||||
plicsw_dev[hartid].plicsw_claim =
|
||||
(void *)base
|
||||
+ PLICSW_CONTEXT_BASE
|
||||
+ PLICSW_CONTEXT_CLAIM
|
||||
+ PLICSW_CONTEXT_PER_HART * hartid;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
46
platform/andes/ae350/plicsw.h
Normal file
46
platform/andes/ae350/plicsw.h
Normal file
|
|
@ -0,0 +1,46 @@
|
|||
/*
|
||||
* SPDX-License-Identifier: BSD-2-Clause
|
||||
*
|
||||
* Copyright (c) 2019 Andes Technology Corporation
|
||||
*
|
||||
* Authors:
|
||||
* Zong Li <zong@andestech.com>
|
||||
* Nylon Chen <nylon7@andestech.com>
|
||||
*/
|
||||
|
||||
#ifndef _AE350_PLICSW_H_
|
||||
#define _AE350_PLICSW_H_
|
||||
|
||||
#define PLICSW_PRIORITY_BASE 0x4
|
||||
|
||||
#define PLICSW_PENDING_BASE 0x1000
|
||||
#define PLICSW_PENDING_PER_HART 0x8
|
||||
|
||||
#define PLICSW_ENABLE_BASE 0x2000
|
||||
#define PLICSW_ENABLE_PER_HART 0x80
|
||||
|
||||
#define PLICSW_CONTEXT_BASE 0x200000
|
||||
#define PLICSW_CONTEXT_PER_HART 0x1000
|
||||
#define PLICSW_CONTEXT_CLAIM 0x4
|
||||
|
||||
#define PLICSW_HART_MASK 0x80808080
|
||||
|
||||
struct plicsw {
|
||||
u32 source_id;
|
||||
|
||||
volatile uint32_t *plicsw_pending;
|
||||
volatile uint32_t *plicsw_enable;
|
||||
volatile uint32_t *plicsw_claim;
|
||||
};
|
||||
|
||||
void plicsw_ipi_send(u32 target_hart);
|
||||
|
||||
void plicsw_ipi_sync(u32 target_hart);
|
||||
|
||||
void plicsw_ipi_clear(u32 target_hart);
|
||||
|
||||
int plicsw_warm_ipi_init(void);
|
||||
|
||||
int plicsw_cold_ipi_init(unsigned long base, u32 hart_count);
|
||||
|
||||
#endif /* _AE350_PLICSW_H_ */
|
||||
97
platform/andes/ae350/plmt.c
Normal file
97
platform/andes/ae350/plmt.c
Normal file
|
|
@ -0,0 +1,97 @@
|
|||
/*
|
||||
* SPDX-License-Identifier: BSD-2-Clause
|
||||
*
|
||||
* Copyright (c) 2019 Andes Technology Corporation
|
||||
*
|
||||
* Authors:
|
||||
* Zong Li <zong@andestech.com>
|
||||
* Nylon Chen <nylon7@andestech.com>
|
||||
*/
|
||||
|
||||
#include <sbi/riscv_io.h>
|
||||
#include <sbi/sbi_hart.h>
|
||||
|
||||
static u32 plmt_time_hart_count;
|
||||
static volatile void *plmt_time_base;
|
||||
static volatile u64 *plmt_time_val;
|
||||
static volatile u64 *plmt_time_cmp;
|
||||
|
||||
u64 plmt_timer_value(void)
|
||||
{
|
||||
#if __riscv_xlen == 64
|
||||
return readq_relaxed(plmt_time_val);
|
||||
#else
|
||||
u32 lo, hi;
|
||||
|
||||
do {
|
||||
hi = readl_relaxed((void *)plmt_time_val + 0x04);
|
||||
lo = readl_relaxed(plmt_time_val);
|
||||
} while (hi != readl_relaxed((void *)plmt_time_val + 0x04));
|
||||
|
||||
return ((u64)hi << 32) | (u64)lo;
|
||||
#endif
|
||||
}
|
||||
|
||||
void plmt_timer_event_stop(void)
|
||||
{
|
||||
u32 target_hart = sbi_current_hartid();
|
||||
|
||||
if (plmt_time_hart_count <= target_hart)
|
||||
return;
|
||||
|
||||
/* Clear PLMT Time Compare */
|
||||
#if __riscv_xlen == 64
|
||||
writeq_relaxed(-1ULL, &plmt_time_cmp[target_hart]);
|
||||
#else
|
||||
writel_relaxed(-1UL, &plmt_time_cmp[target_hart]);
|
||||
writel_relaxed(-1UL, (void *)(&plmt_time_cmp[target_hart]) + 0x04);
|
||||
#endif
|
||||
}
|
||||
|
||||
void plmt_timer_event_start(u64 next_event)
|
||||
{
|
||||
u32 target_hart = sbi_current_hartid();
|
||||
|
||||
if (plmt_time_hart_count <= target_hart)
|
||||
return;
|
||||
|
||||
/* Program PLMT Time Compare */
|
||||
#if __riscv_xlen == 64
|
||||
writeq_relaxed(next_event, &plmt_time_cmp[target_hart]);
|
||||
#else
|
||||
u32 mask = -1UL;
|
||||
|
||||
writel_relaxed(next_event & mask, &plmt_time_cmp[target_hart]);
|
||||
writel_relaxed(next_event >> 32,
|
||||
(void *)(&plmt_time_cmp[target_hart]) + 0x04);
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
int plmt_warm_timer_init(void)
|
||||
{
|
||||
u32 target_hart = sbi_current_hartid();
|
||||
|
||||
if (plmt_time_hart_count <= target_hart || !plmt_time_base)
|
||||
return -1;
|
||||
|
||||
/* Clear PLMT Time Compare */
|
||||
#if __riscv_xlen == 64
|
||||
writeq_relaxed(-1ULL, &plmt_time_cmp[target_hart]);
|
||||
#else
|
||||
writel_relaxed(-1UL, &plmt_time_cmp[target_hart]);
|
||||
writel_relaxed(-1UL, (void *)(&plmt_time_cmp[target_hart]) + 0x04);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int plmt_cold_timer_init(unsigned long base, u32 hart_count)
|
||||
{
|
||||
plmt_time_hart_count = hart_count;
|
||||
plmt_time_base = (void *)base;
|
||||
plmt_time_val = (u64 *)(plmt_time_base);
|
||||
plmt_time_cmp = (u64 *)(plmt_time_base + 0x8);
|
||||
|
||||
return 0;
|
||||
}
|
||||
23
platform/andes/ae350/plmt.h
Normal file
23
platform/andes/ae350/plmt.h
Normal file
|
|
@ -0,0 +1,23 @@
|
|||
/*
|
||||
* SPDX-License-Identifier: BSD-2-Clause
|
||||
*
|
||||
* Copyright (c) 2019 Andes Technology Corporation
|
||||
*
|
||||
* Authors:
|
||||
* Zong Li <zong@andestech.com>
|
||||
*/
|
||||
|
||||
#ifndef _AE350_PLMT_H_
|
||||
#define _AE350_PLMT_H_
|
||||
|
||||
u64 plmt_timer_value(void);
|
||||
|
||||
void plmt_timer_event_stop(void);
|
||||
|
||||
void plmt_timer_event_start(u64 next_event);
|
||||
|
||||
int plmt_warm_timer_init(void);
|
||||
|
||||
int plmt_cold_timer_init(unsigned long base, u32 hart_count);
|
||||
|
||||
#endif /* _AE350_PLMT_H_ */
|
||||
Loading…
Add table
Reference in a new issue