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lib: sbi: Add support for Smepmp
- If Smepmp is enabled, the access flags of an entry are determined based on truth table defined in Smepmp. - First PMP entry (index 0) is reserved. - Existing boot PMP entries start from index 1. - Since enabling Smepmp revokes the access privileges of the M-mode software on S/U-mode region, first PMP entry is used to map/unmap the shared memory between M and S/U-mode. This allows a temporary access window for the M-mode software to read/write to S/U-mode memory region. Signed-off-by: Himanshu Chauhan <hchauhan@ventanamicro.com> Reviewed-by: Anup Patel <anup@brainfault.org>
This commit is contained in:
Himanshu Chauhan
Anup Patel
parent
f3fdd041ac
commit
5dd8db5b10
2 changed files with 129 additions and 18 deletions
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@ -45,6 +45,21 @@ enum sbi_hart_extensions {
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SBI_HART_EXT_MAX,
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};
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/*
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* Smepmp enforces access boundaries between M-mode and
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* S/U-mode. When it is enabled, the PMPs are programmed
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* such that M-mode doesn't have access to S/U-mode memory.
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*
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* To give M-mode R/W access to the shared memory between M and
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* S/U-mode, first entry is reserved. It is disabled at boot.
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* When shared memory access is required, the physical address
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* should be programmed into the first PMP entry with R/W
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* permissions to the M-mode. Once the work is done, it should be
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* unmapped. sbi_hart_map_saddr/sbi_hart_unmap_saddr function
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* pair should be used to map/unmap the shared memory.
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*/
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#define SBI_SMEPMP_RESV_ENTRY 0
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struct sbi_hart_features {
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bool detected;
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int priv_version;
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@ -284,11 +284,75 @@ unsigned int sbi_hart_mhpm_bits(struct sbi_scratch *scratch)
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return hfeatures->mhpm_bits;
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}
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/*
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* Returns Smepmp flags for a given domain and region based on permissions.
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*/
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unsigned int sbi_hart_get_smepmp_flags(struct sbi_scratch *scratch,
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struct sbi_domain *dom,
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struct sbi_domain_memregion *reg)
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{
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unsigned int pmp_flags = 0;
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if (SBI_DOMAIN_MEMREGION_IS_SHARED(reg->flags)) {
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/* Read only for both M and SU modes */
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if (SBI_DOMAIN_MEMREGION_IS_SUR_MR(reg->flags))
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pmp_flags = (PMP_R | PMP_W | PMP_X);
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/* Execute for SU but Read/Execute for M mode */
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else if (SBI_DOMAIN_MEMREGION_IS_SUX_MRX(reg->flags))
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/* locked region */
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pmp_flags = (PMP_L | PMP_W | PMP_X);
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/* Execute only for both M and SU modes */
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else if (SBI_DOMAIN_MEMREGION_IS_SUX_MX(reg->flags))
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pmp_flags = (PMP_L | PMP_W);
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/* Read/Write for both M and SU modes */
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else if (SBI_DOMAIN_MEMREGION_IS_SURW_MRW(reg->flags))
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pmp_flags = (PMP_W | PMP_X);
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/* Read only for SU mode but Read/Write for M mode */
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else if (SBI_DOMAIN_MEMREGION_IS_SUR_MRW(reg->flags))
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pmp_flags = (PMP_W);
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} else if (SBI_DOMAIN_MEMREGION_M_ONLY_ACCESS(reg->flags)) {
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/*
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* When smepmp is supported and used, M region cannot have RWX
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* permissions on any region.
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*/
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if ((reg->flags & SBI_DOMAIN_MEMREGION_M_ACCESS_MASK)
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== SBI_DOMAIN_MEMREGION_M_RWX) {
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sbi_printf("%s: M-mode only regions cannot have"
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"RWX permissions\n", __func__);
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return 0;
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}
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/* M-mode only access regions are always locked */
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pmp_flags |= PMP_L;
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if (reg->flags & SBI_DOMAIN_MEMREGION_M_READABLE)
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pmp_flags |= PMP_R;
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if (reg->flags & SBI_DOMAIN_MEMREGION_M_WRITABLE)
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pmp_flags |= PMP_W;
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if (reg->flags & SBI_DOMAIN_MEMREGION_M_EXECUTABLE)
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pmp_flags |= PMP_X;
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} else if (SBI_DOMAIN_MEMREGION_SU_ONLY_ACCESS(reg->flags)) {
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if (reg->flags & SBI_DOMAIN_MEMREGION_SU_READABLE)
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pmp_flags |= PMP_R;
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if (reg->flags & SBI_DOMAIN_MEMREGION_SU_WRITABLE)
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pmp_flags |= PMP_W;
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if (reg->flags & SBI_DOMAIN_MEMREGION_SU_EXECUTABLE)
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pmp_flags |= PMP_X;
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}
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return pmp_flags;
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}
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int sbi_hart_pmp_configure(struct sbi_scratch *scratch)
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{
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struct sbi_domain_memregion *reg;
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struct sbi_domain *dom = sbi_domain_thishart_ptr();
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unsigned int pmp_idx = 0, pmp_flags, pmp_bits, pmp_gran_log2;
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unsigned int pmp_idx = 0;
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unsigned int pmp_flags, pmp_bits, pmp_gran_log2;
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unsigned int pmp_count = sbi_hart_pmp_count(scratch);
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unsigned long pmp_addr = 0, pmp_addr_max = 0;
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@ -299,36 +363,68 @@ int sbi_hart_pmp_configure(struct sbi_scratch *scratch)
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pmp_bits = sbi_hart_pmp_addrbits(scratch) - 1;
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pmp_addr_max = (1UL << pmp_bits) | ((1UL << pmp_bits) - 1);
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if (sbi_hart_has_extension(scratch, SBI_HART_EXT_SMEPMP)) {
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/* Reserve first entry for dynamic shared mappings */
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pmp_idx = SBI_SMEPMP_RESV_ENTRY + 1;
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/*
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* Set the RLB and clear MML so that, we can write to
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* entries without enforcement even if some entries
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* are locked.
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*/
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csr_set(CSR_MSECCFG, MSECCFG_RLB);
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csr_clear(CSR_MSECCFG, MSECCFG_MML);
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/* Disable the reserved entry */
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pmp_disable(SBI_SMEPMP_RESV_ENTRY);
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}
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sbi_domain_for_each_memregion(dom, reg) {
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if (pmp_count <= pmp_idx)
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break;
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pmp_flags = 0;
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/*
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* If permissions are to be enforced for all modes on this
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* region, the lock bit should be set.
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*/
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if (reg->flags & SBI_DOMAIN_MEMREGION_ENF_PERMISSIONS)
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pmp_flags |= PMP_L;
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if (sbi_hart_has_extension(scratch, SBI_HART_EXT_SMEPMP)) {
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pmp_flags = sbi_hart_get_smepmp_flags(scratch, dom, reg);
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if (reg->flags & SBI_DOMAIN_MEMREGION_SU_READABLE)
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pmp_flags |= PMP_R;
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if (reg->flags & SBI_DOMAIN_MEMREGION_SU_WRITABLE)
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pmp_flags |= PMP_W;
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if (reg->flags & SBI_DOMAIN_MEMREGION_SU_EXECUTABLE)
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pmp_flags |= PMP_X;
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if (pmp_flags == 0)
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return 0;
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} else {
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/*
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* If permissions are to be enforced for all modes on
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* this region, the lock bit should be set.
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*/
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if (reg->flags & SBI_DOMAIN_MEMREGION_ENF_PERMISSIONS)
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pmp_flags |= PMP_L;
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if (reg->flags & SBI_DOMAIN_MEMREGION_SU_READABLE)
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pmp_flags |= PMP_R;
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if (reg->flags & SBI_DOMAIN_MEMREGION_SU_WRITABLE)
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pmp_flags |= PMP_W;
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if (reg->flags & SBI_DOMAIN_MEMREGION_SU_EXECUTABLE)
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pmp_flags |= PMP_X;
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}
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pmp_addr = reg->base >> PMP_SHIFT;
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if (pmp_gran_log2 <= reg->order && pmp_addr < pmp_addr_max)
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if (pmp_gran_log2 <= reg->order && pmp_addr < pmp_addr_max) {
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pmp_set(pmp_idx++, pmp_flags, reg->base, reg->order);
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else {
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sbi_printf("Can not configure pmp for domain %s", dom->name);
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sbi_printf(" because memory region address %lx or size %lx is not in range\n",
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reg->base, reg->order);
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} else {
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sbi_printf("Can not configure pmp for domain %s because"
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" memory region address 0x%lx or size 0x%lx "
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"is not in range.\n", dom->name, reg->base,
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reg->order);
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}
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}
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if (sbi_hart_has_extension(scratch, SBI_HART_EXT_SMEPMP)) {
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/*
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* All entries are programmed. Enable MML bit.
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* Keep the RLB bit so that dynamic mappings can be done.
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*/
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csr_set(CSR_MSECCFG, (MSECCFG_RLB | MSECCFG_MML));
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}
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/*
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* As per section 3.7.2 of privileged specification v1.12,
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* virtual address translations can be speculatively performed
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