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lib: sbi: Remove xchg/cmpxchg implemented via lr/sc
lr/sc is part of the A extension. If the A extension is not supported, lr/sc cannot be used. So remove xchg/cmpxchg. Signed-off-by: Xiang W <wxjstz@126.com> Reviewed-by: Anup Patel <anup@brainfault.org>
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1 changed files with 4 additions and 102 deletions
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@ -12,6 +12,10 @@
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#include <sbi/riscv_atomic.h>
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#include <sbi/riscv_barrier.h>
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#ifndef __riscv_atomic
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#error "opensbi strongly relies on the A extension of RISC-V"
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#endif
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long atomic_read(atomic_t *atom)
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{
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long ret = atom->counter;
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@ -79,131 +83,29 @@ long atomic_sub_return(atomic_t *atom, long value)
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(__typeof__(*(ptr))) __axchg((ptr), _x_, sizeof(*(ptr))); \
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})
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#define __xchg(ptr, new, size) \
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({ \
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__typeof__(ptr) __ptr = (ptr); \
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__typeof__(*(ptr)) __new = (new); \
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__typeof__(*(ptr)) __ret; \
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register unsigned int __rc; \
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switch (size) { \
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case 4: \
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__asm__ __volatile__("0: lr.w %0, %2\n" \
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" sc.w.rl %1, %z3, %2\n" \
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" bnez %1, 0b\n" \
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" fence rw, rw\n" \
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: "=&r"(__ret), "=&r"(__rc), \
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"+A"(*__ptr) \
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: "rJ"(__new) \
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: "memory"); \
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break; \
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case 8: \
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__asm__ __volatile__("0: lr.d %0, %2\n" \
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" sc.d.rl %1, %z3, %2\n" \
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" bnez %1, 0b\n" \
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" fence rw, rw\n" \
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: "=&r"(__ret), "=&r"(__rc), \
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"+A"(*__ptr) \
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: "rJ"(__new) \
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: "memory"); \
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break; \
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default: \
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break; \
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} \
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__ret; \
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})
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#define xchg(ptr, n) \
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({ \
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__typeof__(*(ptr)) _n_ = (n); \
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(__typeof__(*(ptr))) __xchg((ptr), _n_, sizeof(*(ptr))); \
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})
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#define __cmpxchg(ptr, old, new, size) \
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({ \
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__typeof__(ptr) __ptr = (ptr); \
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__typeof__(*(ptr)) __old = (old); \
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__typeof__(*(ptr)) __new = (new); \
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__typeof__(*(ptr)) __ret; \
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register unsigned int __rc; \
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switch (size) { \
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case 4: \
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__asm__ __volatile__("0: lr.w %0, %2\n" \
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" bne %0, %z3, 1f\n" \
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" sc.w.rl %1, %z4, %2\n" \
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" bnez %1, 0b\n" \
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" fence rw, rw\n" \
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"1:\n" \
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: "=&r"(__ret), "=&r"(__rc), \
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"+A"(*__ptr) \
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: "rJ"(__old), "rJ"(__new) \
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: "memory"); \
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break; \
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case 8: \
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__asm__ __volatile__("0: lr.d %0, %2\n" \
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" bne %0, %z3, 1f\n" \
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" sc.d.rl %1, %z4, %2\n" \
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" bnez %1, 0b\n" \
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" fence rw, rw\n" \
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"1:\n" \
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: "=&r"(__ret), "=&r"(__rc), \
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"+A"(*__ptr) \
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: "rJ"(__old), "rJ"(__new) \
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: "memory"); \
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break; \
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default: \
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break; \
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} \
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__ret; \
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})
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#define cmpxchg(ptr, o, n) \
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({ \
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__typeof__(*(ptr)) _o_ = (o); \
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__typeof__(*(ptr)) _n_ = (n); \
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(__typeof__(*(ptr))) \
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__cmpxchg((ptr), _o_, _n_, sizeof(*(ptr))); \
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})
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long atomic_cmpxchg(atomic_t *atom, long oldval, long newval)
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{
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#ifdef __riscv_atomic
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return __sync_val_compare_and_swap(&atom->counter, oldval, newval);
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#else
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return cmpxchg(&atom->counter, oldval, newval);
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#endif
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}
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long atomic_xchg(atomic_t *atom, long newval)
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{
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/* Atomically set new value and return old value. */
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#ifdef __riscv_atomic
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return axchg(&atom->counter, newval);
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#else
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return xchg(&atom->counter, newval);
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#endif
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}
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unsigned int atomic_raw_xchg_uint(volatile unsigned int *ptr,
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unsigned int newval)
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{
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/* Atomically set new value and return old value. */
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#ifdef __riscv_atomic
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return axchg(ptr, newval);
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#else
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return xchg(ptr, newval);
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#endif
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}
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unsigned long atomic_raw_xchg_ulong(volatile unsigned long *ptr,
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unsigned long newval)
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{
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/* Atomically set new value and return old value. */
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#ifdef __riscv_atomic
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return axchg(ptr, newval);
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#else
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return xchg(ptr, newval);
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#endif
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}
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#if (__SIZEOF_POINTER__ == 8)
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