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docs: platform: Add documentation for Renesas RZ/Five SoC
This patch adds documentation to build Renesas RZ/Five (R9A07G043F) SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Anup Patel <anup@brainfault.org>
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Lad Prabhakar
Anup Patel
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7a3354ac15
3 changed files with 167 additions and 0 deletions
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@ -47,6 +47,7 @@ RISC-V Platforms Using Generic Platform
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* **Andes AE350 Platform** (*[andes-ae350.md]*)
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* **QEMU RISC-V Virt Machine** (*[qemu_virt.md]*)
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* **Renesas RZ/Five SoC** (*[renesas-rzfive.md]*)
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* **Shakti C-class SoC Platform** (*[shakti_cclass.md]*)
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* **SiFive HiFive Unleashed** (*[sifive_fu540.md]*)
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* **Spike** (*[spike.md]*)
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@ -54,6 +55,7 @@ RISC-V Platforms Using Generic Platform
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[andes-ae350.md]: andse-ae350.md
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[qemu_virt.md]: qemu_virt.md
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[renesas-rzfive.md]: renesas-rzfive.md
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[shakti_cclass.md]: shakti_cclass.md
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[sifive_fu540.md]: sifive_fu540.md
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[spike.md]: spike.md
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@ -39,6 +39,10 @@ OpenSBI currently supports the following virtual and hardware platforms:
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processor based SOCs. More details on this platform can be found in the
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file *[shakti_cclass.md]*.
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* **Renesas RZ/Five SoC**: Platform support for Renesas RZ/Five (R9A07G043F) SoC
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used on the Renesas RZ/Five SMARC EVK board. More details on this platform can
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be found in the file *[renesas-rzfive.md]*.
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The code for these supported platforms can be used as example to implement
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support for other platforms. The *platform/template* directory also provides
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template files for implementing support for a new platform. The *objects.mk*,
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@ -54,3 +58,4 @@ comments to facilitate the implementation.
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[spike.md]: spike.md
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[fpga-openpiton.md]: fpga-openpiton.md
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[shakti_cclass.md]: shakti_cclass.md
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[renesas-rzfive.md]: renesas-rzfive.md
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160
docs/platform/renesas-rzfive.md
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160
docs/platform/renesas-rzfive.md
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@ -0,0 +1,160 @@
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Renesas RZ/Five SoC (R9A07G043F) Platform
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=========================================
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The RZ/Five microprocessor includes a single RISC-V CPU Core (Andes AX45MP)
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1.0 GHz, 16-bit DDR3L/DDR4 interface. Supported interfaces include:
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- Memory controller for DDR4-1600 / DDR3L-1333 with 16 bits
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- System RAM (RAM of 128 Kbytes (ECC))
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- SPI Multi I/O Bus Controller 1ch
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- SD Card Host Interface/Multimedia Card Interface (SD/MMC) 2ch
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- Serial Sound Interface (SSI) 4ch
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- Sampling Rate Converter (SRC) 1ch
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- USB2.0 host/function interface 2ch (ch0: Host-Function ch1: Host only)
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- Gigabit Ethernet Interface (GbE) 2ch
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- Controller Area Network Interface (CAN) 2ch (CAN-FD ISO 11898-1 (CD2014) compliant)
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- Multi-function Timer Pulse Unit 3 (MTU3a) 9 ch (16 bits × 8 channels, 32 bits × 1 channel)
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- Port Output Enable 3 (POE3)
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- Watchdog Timer (WDT) 1ch
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- General Timer (GTM) 3ch (32bits)
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- I2C Bus Interface (I2C) 4ch
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- Serial Communication Interface with FIFO (SCIFA) 5ch
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- Serial Communication Interface (SCI) 2ch
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- Renesas Serial Peripheral Interface (RSPI) 3ch
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- A/D Converter (ADC) 2ch
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making it ideal for applications such as entry-class social infrastructure
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gateway control and industrial gateway control. More details can be found at
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below link [0].
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[0] https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-mpus/rzfive-general-purpose-microprocessors-risc-v-cpu-core-andes-ax45mp-single-10-ghz-2ch-gigabit-ethernet
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To build platform specific library and firmwares, provide the
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*PLATFORM=generic* parameter to the top level make command.
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Platform Options
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----------------
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The Renesas RZ/Five platform does not have any platform-specific options.
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Building Renesas RZ/Five Platform
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---------------------------------
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```
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make PLATFORM=generic
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```
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DTS Example: (RZ/Five AX45MP)
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-----------------------------
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```
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compatible = "renesas,r9a07g043f01", "renesas,r9a07g043";
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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timebase-frequency = <12000000>;
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cpu0: cpu@0 {
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compatible = "andestech,ax45mp", "riscv";
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device_type = "cpu";
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reg = <0x0>;
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status = "okay";
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riscv,isa = "rv64imafdc";
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mmu-type = "riscv,sv39";
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i-cache-size = <0x8000>;
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i-cache-line-size = <0x40>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <0x40>;
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clocks = <&cpg CPG_CORE R9A07G043_CLK_I>;
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cpu0_intc: interrupt-controller {
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#interrupt-cells = <1>;
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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};
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};
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <0>;
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ranges;
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scif0: serial@1004b800 {
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compatible = "renesas,scif-r9a07g043",
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"renesas,scif-r9a07g044";
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reg = <0 0x1004b800 0 0x400>;
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interrupts = <412 IRQ_TYPE_LEVEL_HIGH>,
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<414 IRQ_TYPE_LEVEL_HIGH>,
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<415 IRQ_TYPE_LEVEL_HIGH>,
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<413 IRQ_TYPE_LEVEL_HIGH>,
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<416 IRQ_TYPE_LEVEL_HIGH>,
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<416 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "eri", "rxi", "txi",
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"bri", "dri", "tei";
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clocks = <&cpg CPG_MOD R9A07G043_SCIF0_CLK_PCK>;
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clock-names = "fck";
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power-domains = <&cpg>;
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resets = <&cpg R9A07G043_SCIF0_RST_SYSTEM_N>;
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status = "disabled";
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};
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cpg: clock-controller@11010000 {
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compatible = "renesas,r9a07g043-cpg";
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reg = <0 0x11010000 0 0x10000>;
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clocks = <&extal_clk>;
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clock-names = "extal";
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#clock-cells = <2>;
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#reset-cells = <1>;
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#power-domain-cells = <0>;
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};
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sysc: system-controller@11020000 {
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compatible = "renesas,r9a07g043-sysc";
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reg = <0 0x11020000 0 0x10000>;
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status = "disabled";
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};
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pinctrl: pinctrl@11030000 {
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compatible = "renesas,r9a07g043-pinctrl";
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reg = <0 0x11030000 0 0x10000>;
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gpio-controller;
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#gpio-cells = <2>;
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#interrupt-cells = <2>;
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interrupt-controller;
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gpio-ranges = <&pinctrl 0 0 152>;
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clocks = <&cpg CPG_MOD R9A07G043_GPIO_HCLK>;
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power-domains = <&cpg>;
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resets = <&cpg R9A07G043_GPIO_RSTN>,
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<&cpg R9A07G043_GPIO_PORT_RESETN>,
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<&cpg R9A07G043_GPIO_SPARE_RESETN>;
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};
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plmt0: plmt0@110c0000 {
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compatible = "andestech,plmt0", "riscv,plmt0";
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reg = <0x0 0x110c0000 0x0 0x10000>;
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interrupts-extended = <&cpu0_intc 7>;
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};
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plic: interrupt-controller@12c00000 {
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compatible = "renesas,r9a07g043-plic", "andestech,nceplic100";
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#interrupt-cells = <2>;
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#address-cells = <0>;
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riscv,ndev = <511>;
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interrupt-controller;
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reg = <0x0 0x12c00000 0x0 0x400000>;
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clocks = <&cpg CPG_MOD R9A07G043_NCEPLIC_ACLK>;
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power-domains = <&cpg>;
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resets = <&cpg R9A07G043_NCEPLIC_ARESETN>;
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interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9>;
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};
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plicsw: interrupt-controller@13000000 {
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compatible = "andestech,plicsw";
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reg = <0x0 0x13000000 0x0 0x400000>;
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interrupts-extended = <&cpu0_intc 3>;
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interrupt-controller;
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#address-cells = <2>;
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#interrupt-cells = <2>;
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};
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};
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```
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