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include: Make sbi_current_hartid() as macro in riscv_asm.h
The sbi_current_hartid() being a regular function is quite expensive because for callers it is a function call instead of a direct CSR read. This patch converts sbi_current_hartid() into a macro in riscv_asm.h. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
This commit is contained in:
parent
16e7071f6d
commit
823345ecae
20 changed files with 49 additions and 52 deletions
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@ -157,6 +157,8 @@ void csr_write_num(int csr_num, unsigned long val);
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__asm__ __volatile__("wfi" ::: "memory"); \
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} while (0)
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/* Get current HART id */
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#define current_hartid() ((unsigned int)csr_read(CSR_MHARTID))
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/* determine CPU extension, return non-zero support */
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int misa_extension_imp(char ext);
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@ -32,6 +32,4 @@ sbi_hart_switch_mode(unsigned long arg0, unsigned long arg1,
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unsigned long next_addr, unsigned long next_mode,
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bool next_virt);
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u32 sbi_current_hartid(void);
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#endif
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@ -8,6 +8,7 @@
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* Atish Patra <atish.patra@wdc.com>
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*/
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#include <sbi/riscv_asm.h>
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#include <sbi/sbi_console.h>
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#include <sbi/sbi_ecall.h>
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#include <sbi/sbi_ecall_interface.h>
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@ -46,7 +47,7 @@ static int sbi_ecall_legacy_handler(struct sbi_scratch *scratch,
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{
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int ret = 0;
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struct sbi_tlb_info tlb_info;
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u32 source_hart = sbi_current_hartid();
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u32 source_hart = current_hartid();
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ulong hmask = 0;
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switch (extid) {
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@ -8,6 +8,7 @@
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* Atish Patra <atish.patra@wdc.com>
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*/
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#include <sbi/riscv_asm.h>
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#include <sbi/sbi_ecall.h>
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#include <sbi/sbi_ecall_interface.h>
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#include <sbi/sbi_error.h>
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@ -15,7 +16,6 @@
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#include <sbi/sbi_ipi.h>
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#include <sbi/sbi_timer.h>
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#include <sbi/sbi_tlb.h>
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#include <sbi/riscv_asm.h>
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static int sbi_ecall_time_handler(struct sbi_scratch *scratch,
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unsigned long extid, unsigned long funcid,
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@ -50,7 +50,7 @@ static int sbi_ecall_rfence_handler(struct sbi_scratch *scratch,
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{
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int ret = 0;
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struct sbi_tlb_info tlb_info;
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u32 source_hart = sbi_current_hartid();
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u32 source_hart = current_hartid();
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if (funcid >= SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA &&
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funcid <= SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASID)
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@ -17,14 +17,6 @@
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#include <sbi/sbi_hart.h>
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#include <sbi/sbi_platform.h>
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/**
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* Return HART ID of the caller.
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*/
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unsigned int sbi_current_hartid()
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{
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return (u32)csr_read(CSR_MHARTID);
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}
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static void mstatus_init(struct sbi_scratch *scratch, u32 hartid)
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{
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const struct sbi_platform *plat = sbi_platform_ptr(scratch);
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@ -204,7 +204,7 @@ void __noreturn sbi_hsm_exit(struct sbi_scratch *scratch)
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fail_exit:
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/* It should never reach here */
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sbi_printf("ERR: Failed stop hart [%u]\n", sbi_current_hartid());
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sbi_printf("ERR: Failed stop hart [%u]\n", current_hartid());
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sbi_hart_hang();
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}
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@ -256,7 +256,7 @@ int sbi_hsm_hart_start(struct sbi_scratch *scratch, u32 hartid,
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int sbi_hsm_hart_stop(struct sbi_scratch *scratch, bool exitnow)
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{
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int oldstate;
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u32 hartid = sbi_current_hartid();
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u32 hartid = current_hartid();
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const struct sbi_platform *plat = sbi_platform_ptr(scratch);
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struct sbi_hsm_data *hdata = sbi_scratch_offset_ptr(scratch,
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hart_data_offset);
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@ -273,7 +273,7 @@ static atomic_t coldboot_lottery = ATOMIC_INITIALIZER(0);
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void __noreturn sbi_init(struct sbi_scratch *scratch)
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{
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bool coldboot = FALSE;
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u32 hartid = sbi_current_hartid();
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u32 hartid = current_hartid();
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const struct sbi_platform *plat = sbi_platform_ptr(scratch);
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if ((SBI_HARTMASK_MAX_BITS <= hartid) ||
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@ -316,7 +316,7 @@ unsigned long sbi_init_count(u32 hartid)
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*/
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void __noreturn sbi_exit(struct sbi_scratch *scratch)
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{
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u32 hartid = sbi_current_hartid();
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u32 hartid = current_hartid();
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const struct sbi_platform *plat = sbi_platform_ptr(scratch);
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if (sbi_platform_hart_disabled(plat, hartid))
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@ -176,7 +176,7 @@ void sbi_ipi_process(struct sbi_scratch *scratch)
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struct sbi_ipi_data *ipi_data =
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sbi_scratch_offset_ptr(scratch, ipi_data_off);
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u32 hartid = sbi_current_hartid();
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u32 hartid = current_hartid();
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sbi_platform_ipi_clear(plat, hartid);
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ipi_type = atomic_raw_xchg_ulong(&ipi_data->ipi_type, 0);
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@ -8,6 +8,7 @@
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* Nick Kossifidis <mick@ics.forth.gr>
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*/
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#include <sbi/riscv_asm.h>
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#include <sbi/sbi_bitops.h>
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#include <sbi/sbi_hart.h>
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#include <sbi/sbi_hsm.h>
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@ -39,12 +40,12 @@ void sbi_system_final_exit(struct sbi_scratch *scratch)
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void __noreturn sbi_system_reboot(struct sbi_scratch *scratch, u32 type)
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{
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ulong hbase = 0, hmask;
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u32 current_hartid = sbi_current_hartid();
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u32 cur_hartid = current_hartid();
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/* Send HALT IPI to every hart other than the current hart */
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while (!sbi_hsm_hart_started_mask(scratch, hbase, &hmask)) {
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if (hbase <= current_hartid)
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hmask &= ~(1UL << (current_hartid - hbase));
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if (hbase <= cur_hartid)
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hmask &= ~(1UL << (cur_hartid - hbase));
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if (hmask)
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sbi_ipi_send_halt(scratch, hmask, hbase);
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hbase += BITS_PER_LONG;
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@ -63,12 +64,12 @@ void __noreturn sbi_system_reboot(struct sbi_scratch *scratch, u32 type)
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void __noreturn sbi_system_shutdown(struct sbi_scratch *scratch, u32 type)
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{
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ulong hbase = 0, hmask;
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u32 current_hartid = sbi_current_hartid();
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u32 cur_hartid = current_hartid();
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/* Send HALT IPI to every hart other than the current hart */
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while (!sbi_hsm_hart_started_mask(scratch, hbase, &hmask)) {
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if (hbase <= current_hartid)
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hmask &= ~(1UL << (current_hartid - hbase));
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if (hbase <= cur_hartid)
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hmask &= ~(1UL << (cur_hartid - hbase));
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if (hmask)
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sbi_ipi_send_halt(scratch, hmask, hbase);
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hbase += BITS_PER_LONG;
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@ -319,7 +319,7 @@ static int sbi_tlb_update(struct sbi_scratch *scratch,
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int ret;
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struct sbi_fifo *tlb_fifo_r;
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struct sbi_tlb_info *tinfo = data;
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u32 curr_hartid = sbi_current_hartid();
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u32 curr_hartid = current_hartid();
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/*
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* If address range to flush is too big then simply
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@ -217,7 +217,7 @@ void sbi_trap_handler(struct sbi_trap_regs *regs,
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{
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int rc = SBI_ENOTSUPP;
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const char *msg = "trap handler failed";
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u32 hartid = sbi_current_hartid();
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u32 hartid = current_hartid();
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ulong mcause = csr_read(CSR_MCAUSE);
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ulong mtval = csr_read(CSR_MTVAL), mtval2 = 0, mtinst = 0;
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struct sbi_trap_info trap, *uptrap;
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@ -7,9 +7,9 @@
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* Anup Patel <anup.patel@wdc.com>
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*/
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#include <sbi/riscv_io.h>
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#include <sbi/riscv_asm.h>
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#include <sbi/riscv_atomic.h>
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#include <sbi/sbi_hart.h>
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#include <sbi/riscv_io.h>
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#include <sbi_utils/sys/clint.h>
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static u32 clint_ipi_hart_count;
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int clint_warm_ipi_init(void)
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{
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u32 hartid = sbi_current_hartid();
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u32 hartid = current_hartid();
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if (!clint_ipi_base)
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return -1;
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@ -105,7 +105,7 @@ u64 clint_timer_value(void)
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void clint_timer_event_stop(void)
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{
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u32 target_hart = sbi_current_hartid();
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u32 target_hart = current_hartid();
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if (clint_time_hart_count <= target_hart)
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return;
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void clint_timer_event_start(u64 next_event)
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{
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u32 target_hart = sbi_current_hartid();
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u32 target_hart = current_hartid();
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if (clint_time_hart_count <= target_hart)
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return;
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int clint_warm_timer_init(void)
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{
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u32 target_hart = sbi_current_hartid();
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u32 target_hart = current_hartid();
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if (clint_time_hart_count <= target_hart || !clint_time_base)
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return -1;
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@ -8,9 +8,9 @@
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* Nylon Chen <nylon7@andestech.com>
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*/
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#include <sbi/riscv_asm.h>
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#include <sbi/riscv_encoding.h>
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#include <sbi/sbi_const.h>
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#include <sbi/sbi_hart.h>
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#include <sbi/sbi_platform.h>
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#include <sbi/sbi_console.h>
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#include <sbi_utils/serial/uart8250.h>
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/* Initialize the platform interrupt controller for current HART. */
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static int ae350_irqchip_init(bool cold_boot)
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{
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u32 hartid = sbi_current_hartid();
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u32 hartid = current_hartid();
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int ret;
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if (cold_boot) {
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@ -8,9 +8,9 @@
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* Nylon Chen <nylon7@andestech.com>
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*/
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#include <sbi/sbi_types.h>
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#include <sbi/sbi_hart.h>
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#include <sbi/riscv_asm.h>
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#include <sbi/riscv_io.h>
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#include <sbi/sbi_types.h>
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#include "plicsw.h"
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#include "platform.h"
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@ -19,7 +19,7 @@ static struct plicsw plicsw_dev[AE350_HART_COUNT];
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static inline void plicsw_claim(void)
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{
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u32 source_hart = sbi_current_hartid();
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u32 source_hart = current_hartid();
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plicsw_dev[source_hart].source_id =
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readl(plicsw_dev[source_hart].plicsw_claim);
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@ -27,7 +27,7 @@ static inline void plicsw_claim(void)
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static inline void plicsw_complete(void)
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{
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u32 source_hart = sbi_current_hartid();
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u32 source_hart = current_hartid();
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u32 source = plicsw_dev[source_hart].source_id;
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writel(source, plicsw_dev[source_hart].plicsw_claim);
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@ -61,7 +61,7 @@ static inline void plic_sw_pending(u32 target_hart)
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* The bit 5 is used to send IPI to hart 2
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* The bit 4 is used to send IPI to hart 3
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*/
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u32 source_hart = sbi_current_hartid();
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u32 source_hart = current_hartid();
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u32 target_offset = (PLICSW_PENDING_PER_HART - 1) - target_hart;
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u32 per_hart_offset = PLICSW_PENDING_PER_HART * source_hart;
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u32 val = 1 << target_offset << per_hart_offset;
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int plicsw_warm_ipi_init(void)
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{
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u32 hartid = sbi_current_hartid();
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u32 hartid = current_hartid();
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if (!plicsw_dev[hartid].plicsw_pending
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&& !plicsw_dev[hartid].plicsw_enable
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@ -8,8 +8,8 @@
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* Nylon Chen <nylon7@andestech.com>
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*/
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#include <sbi/riscv_asm.h>
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#include <sbi/riscv_io.h>
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#include <sbi/sbi_hart.h>
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static u32 plmt_time_hart_count;
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static volatile void *plmt_time_base;
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void plmt_timer_event_stop(void)
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{
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u32 target_hart = sbi_current_hartid();
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u32 target_hart = current_hartid();
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if (plmt_time_hart_count <= target_hart)
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return;
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void plmt_timer_event_start(u64 next_event)
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{
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u32 target_hart = sbi_current_hartid();
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u32 target_hart = current_hartid();
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if (plmt_time_hart_count <= target_hart)
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return;
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int plmt_warm_timer_init(void)
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{
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u32 target_hart = sbi_current_hartid();
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u32 target_hart = current_hartid();
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if (plmt_time_hart_count <= target_hart || !plmt_time_base)
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return -1;
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@ -4,6 +4,7 @@
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* Panagiotis Peristerakis <perister@ics.forth.gr>
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*/
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#include <sbi/riscv_asm.h>
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#include <sbi/riscv_encoding.h>
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#include <sbi/sbi_const.h>
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#include <sbi/sbi_platform.h>
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@ -105,7 +106,7 @@ static int plic_ariane_warm_irqchip_init(u32 target_hart,
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*/
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static int ariane_irqchip_init(bool cold_boot)
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{
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u32 hartid = sbi_current_hartid();
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u32 hartid = current_hartid();
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int ret;
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if (cold_boot) {
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@ -7,9 +7,9 @@
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* Damien Le Moal <damien.lemoal@wdc.com>
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*/
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#include <sbi/riscv_asm.h>
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#include <sbi/riscv_encoding.h>
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#include <sbi/sbi_const.h>
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#include <sbi/sbi_hart.h>
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#include <sbi/sbi_platform.h>
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#include <sbi/sbi_console.h>
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#include <sbi_utils/irqchip/plic.h>
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@ -55,7 +55,7 @@ static int k210_console_init(void)
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static int k210_irqchip_init(bool cold_boot)
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{
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int rc;
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u32 hartid = sbi_current_hartid();
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u32 hartid = current_hartid();
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if (cold_boot) {
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rc = plic_cold_irqchip_init(K210_PLIC_BASE_ADDR,
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@ -8,6 +8,7 @@
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* Nick Kossifidis <mick@ics.forth.gr>
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*/
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#include <sbi/riscv_asm.h>
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#include <sbi/riscv_encoding.h>
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#include <sbi/riscv_io.h>
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#include <sbi/sbi_const.h>
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@ -84,7 +85,7 @@ static int virt_console_init(void)
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static int virt_irqchip_init(bool cold_boot)
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{
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int rc;
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u32 hartid = sbi_current_hartid();
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u32 hartid = current_hartid();
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if (cold_boot) {
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rc = plic_cold_irqchip_init(
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@ -9,12 +9,12 @@
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#include <libfdt.h>
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#include <fdt.h>
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#include <sbi/riscv_asm.h>
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#include <sbi/riscv_io.h>
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#include <sbi/riscv_encoding.h>
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#include <sbi/sbi_const.h>
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#include <sbi/sbi_hart.h>
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#include <sbi/sbi_console.h>
|
||||
#include <sbi/sbi_platform.h>
|
||||
#include <sbi/riscv_io.h>
|
||||
#include <sbi_utils/irqchip/plic.h>
|
||||
#include <sbi_utils/serial/sifive-uart.h>
|
||||
#include <sbi_utils/sys/clint.h>
|
||||
|
@ -148,7 +148,7 @@ static int fu540_console_init(void)
|
|||
static int fu540_irqchip_init(bool cold_boot)
|
||||
{
|
||||
int rc;
|
||||
u32 hartid = sbi_current_hartid();
|
||||
u32 hartid = current_hartid();
|
||||
|
||||
if (cold_boot) {
|
||||
rc = plic_cold_irqchip_init(FU540_PLIC_ADDR,
|
||||
|
|
|
@ -4,6 +4,7 @@
|
|||
* Copyright (c) 2019 Western Digital Corporation or its affiliates.
|
||||
*/
|
||||
|
||||
#include <sbi/riscv_asm.h>
|
||||
#include <sbi/riscv_encoding.h>
|
||||
#include <sbi/sbi_const.h>
|
||||
#include <sbi/sbi_platform.h>
|
||||
|
@ -82,7 +83,7 @@ static int platform_console_getc(void)
|
|||
*/
|
||||
static int platform_irqchip_init(bool cold_boot)
|
||||
{
|
||||
u32 hartid = sbi_current_hartid();
|
||||
u32 hartid = current_hartid();
|
||||
int ret;
|
||||
|
||||
/* Example if the generic PLIC driver is used */
|
||||
|
|
Loading…
Add table
Reference in a new issue