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platform: generic: thead: separate implement of T-HEAD c9xx pmu
Separate the implement of T-HEAD c9xx pmu to allow any platform with c9xx cores can use it. Signed-off-by: Inochi Amaoto <inochiama@outlook.com> Reviewed-by: Anup Patel <anup@brainfault.org>
This commit is contained in:
parent
c1a6987447
commit
8e941e7fe3
6 changed files with 87 additions and 49 deletions
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@ -26,6 +26,7 @@ config PLATFORM_GENERIC_MINOR_VER
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config PLATFORM_ALLWINNER_D1
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bool "Allwinner D1 support"
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depends on FDT_IRQCHIP_PLIC
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select THEAD_C9XX_PMU
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default n
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config PLATFORM_ANDES_AE350
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@ -57,5 +58,6 @@ config PLATFORM_THEAD
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default n
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source "$(OPENSBI_SRC_DIR)/platform/generic/andes/Kconfig"
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source "$(OPENSBI_SRC_DIR)/platform/generic/thead/Kconfig"
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endif
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@ -6,6 +6,7 @@
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#include <platform_override.h>
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#include <thead/c9xx_encoding.h>
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#include <thead/c9xx_pmu.h>
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#include <sbi/riscv_asm.h>
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#include <sbi/riscv_io.h>
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#include <sbi/sbi_bitops.h>
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@ -223,58 +224,10 @@ static int sun20i_d1_fdt_fixup(void *fdt, const struct fdt_match *match)
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return fdt_add_cpu_idle_states(fdt, sun20i_d1_cpu_idle_states);
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}
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static void thead_c9xx_pmu_ctr_enable_irq(uint32_t ctr_idx)
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{
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if (ctr_idx >= SBI_PMU_HW_CTR_MAX)
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return;
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/**
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* Clear out the OF bit so that next interrupt can be enabled.
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* This should be done before starting interrupt to avoid unexcepted
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* overflow interrupt.
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*/
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csr_clear(THEAD_C9XX_CSR_MCOUNTEROF, BIT(ctr_idx));
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/**
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* This register is described in C9xx document as the control register
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* for enabling writes to the superuser state counter. However, if the
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* corresponding bit is not set to 1, scounterof will always read as 0
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* when the counter register overflows.
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*/
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csr_set(THEAD_C9XX_CSR_MCOUNTERWEN, BIT(ctr_idx));
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/**
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* SSCOFPMF uses the OF bit for enabling/disabling the interrupt,
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* while the C9XX has designated enable bits.
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* So enable per-counter interrupt on C9xx here.
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*/
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csr_set(THEAD_C9XX_CSR_MCOUNTERINTEN, BIT(ctr_idx));
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}
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static void thead_c9xx_pmu_ctr_disable_irq(uint32_t ctr_idx)
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{
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/**
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* There is no need to clear the bit of mcounterwen, it will expire
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* after setting the csr mcountinhibit.
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*/
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csr_clear(THEAD_C9XX_CSR_MCOUNTERINTEN, BIT(ctr_idx));
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}
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static int thead_c9xx_pmu_irq_bit(void)
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{
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return THEAD_C9XX_MIP_MOIP;
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}
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const struct sbi_pmu_device thead_c9xx_pmu_device = {
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.hw_counter_enable_irq = thead_c9xx_pmu_ctr_enable_irq,
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.hw_counter_disable_irq = thead_c9xx_pmu_ctr_disable_irq,
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.hw_counter_irq_bit = thead_c9xx_pmu_irq_bit,
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};
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static int sun20i_d1_extensions_init(const struct fdt_match *match,
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struct sbi_hart_features *hfeatures)
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{
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sbi_pmu_set_device(&thead_c9xx_pmu_device);
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thead_c9xx_register_pmu_device();
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/* auto-detection doesn't work on t-head c9xx cores */
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/* D1 has 29 mhpmevent csrs, but only 3-9,13-17 have valid value */
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7
platform/generic/include/thead/c9xx_pmu.h
Normal file
7
platform/generic/include/thead/c9xx_pmu.h
Normal file
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@ -0,0 +1,7 @@
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#ifndef __RISCV_THEAD_C9XX_PMU_H____
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#define __RISCV_THEAD_C9XX_PMU_H____
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void thead_c9xx_register_pmu_device(void);
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#endif // __RISCV_THEAD_C9XX_PMU_H____
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5
platform/generic/thead/Kconfig
Normal file
5
platform/generic/thead/Kconfig
Normal file
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@ -0,0 +1,5 @@
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# SPDX-License-Identifier: BSD-2-Clause
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config THEAD_C9XX_PMU
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bool "T-HEAD c9xx M-mode PMU support"
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default n
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@ -5,6 +5,8 @@
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# Copyright (C) 2023 Alibaba Group Holding Limited.
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#
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platform-objs-$(CONFIG_THEAD_C9XX_PMU) += thead/thead_c9xx_pmu.o
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carray-platform_override_modules-$(CONFIG_PLATFORM_THEAD) += thead_generic
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platform-objs-$(CONFIG_PLATFORM_THEAD) += thead/thead-generic.o
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platform-objs-$(CONFIG_PLATFORM_THEAD) += thead/thead-trap-handler.o
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69
platform/generic/thead/thead_c9xx_pmu.c
Normal file
69
platform/generic/thead/thead_c9xx_pmu.c
Normal file
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@ -0,0 +1,69 @@
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/*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Authors:
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* Inochi Amaoto <inochiama@outlook.com>
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* Haijiao Liu <haijiao.liu@sophgo.com>
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*
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*/
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#include <thead/c9xx_encoding.h>
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#include <thead/c9xx_pmu.h>
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#include <sbi/riscv_asm.h>
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#include <sbi/sbi_bitops.h>
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#include <sbi/sbi_ecall_interface.h>
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#include <sbi/sbi_pmu.h>
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static void thead_c9xx_pmu_ctr_enable_irq(uint32_t ctr_idx)
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{
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if (ctr_idx >= SBI_PMU_HW_CTR_MAX)
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return;
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/**
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* Clear out the OF bit so that next interrupt can be enabled.
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* This should be done before starting interrupt to avoid unexcepted
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* overflow interrupt.
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*/
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csr_clear(THEAD_C9XX_CSR_MCOUNTEROF, BIT(ctr_idx));
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/**
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* This register is described in C9xx document as the control register
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* for enabling writes to the superuser state counter. However, if the
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* corresponding bit is not set to 1, scounterof will always read as 0
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* when the counter register overflows.
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*/
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csr_set(THEAD_C9XX_CSR_MCOUNTERWEN, BIT(ctr_idx));
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/**
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* SSCOFPMF uses the OF bit for enabling/disabling the interrupt,
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* while the C9XX has designated enable bits.
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* So enable per-counter interrupt on C9xx here.
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*/
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csr_set(THEAD_C9XX_CSR_MCOUNTERINTEN, BIT(ctr_idx));
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}
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static void thead_c9xx_pmu_ctr_disable_irq(uint32_t ctr_idx)
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{
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/**
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* There is no need to clear the bit of mcounterwen, it will expire
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* after setting the csr mcountinhibit.
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*/
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csr_clear(THEAD_C9XX_CSR_MCOUNTERINTEN, BIT(ctr_idx));
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}
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static int thead_c9xx_pmu_irq_bit(void)
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{
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return THEAD_C9XX_MIP_MOIP;
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}
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static const struct sbi_pmu_device thead_c9xx_pmu_device = {
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.name = "thead,c900-pmu",
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.hw_counter_enable_irq = thead_c9xx_pmu_ctr_enable_irq,
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.hw_counter_disable_irq = thead_c9xx_pmu_ctr_disable_irq,
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.hw_counter_irq_bit = thead_c9xx_pmu_irq_bit,
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};
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void thead_c9xx_register_pmu_device(void)
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{
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sbi_pmu_set_device(&thead_c9xx_pmu_device);
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}
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