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lib: Move instruction encoding macros to riscv_encoding.h
This patch moves all instruction encoding macros to riscv_encoding.h. Signed-off-by: Anup Patel <anup.patel@wdc.com>
This commit is contained in:
Anup Patel
Anup Patel
parent
fd7199920e
commit
96f66f79ca
3 changed files with 117 additions and 65 deletions
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@ -420,4 +420,121 @@
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#define CAUSE_LOAD_PAGE_FAULT 0xd
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#define CAUSE_STORE_PAGE_FAULT 0xf
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#define INSN_MATCH_LB 0x3
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#define INSN_MASK_LB 0x707f
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#define INSN_MATCH_LH 0x1003
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#define INSN_MASK_LH 0x707f
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#define INSN_MATCH_LW 0x2003
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#define INSN_MASK_LW 0x707f
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#define INSN_MATCH_LD 0x3003
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#define INSN_MASK_LD 0x707f
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#define INSN_MATCH_LBU 0x4003
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#define INSN_MASK_LBU 0x707f
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#define INSN_MATCH_LHU 0x5003
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#define INSN_MASK_LHU 0x707f
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#define INSN_MATCH_LWU 0x6003
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#define INSN_MASK_LWU 0x707f
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#define INSN_MATCH_SB 0x23
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#define INSN_MASK_SB 0x707f
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#define INSN_MATCH_SH 0x1023
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#define INSN_MASK_SH 0x707f
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#define INSN_MATCH_SW 0x2023
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#define INSN_MASK_SW 0x707f
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#define INSN_MATCH_SD 0x3023
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#define INSN_MASK_SD 0x707f
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#define INSN_MATCH_C_LD 0x6000
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#define INSN_MASK_C_LD 0xe003
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#define INSN_MATCH_C_SD 0xe000
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#define INSN_MASK_C_SD 0xe003
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#define INSN_MATCH_C_LW 0x4000
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#define INSN_MASK_C_LW 0xe003
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#define INSN_MATCH_C_SW 0xc000
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#define INSN_MASK_C_SW 0xe003
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#define INSN_MATCH_C_LDSP 0x6002
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#define INSN_MASK_C_LDSP 0xe003
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#define INSN_MATCH_C_SDSP 0xe002
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#define INSN_MASK_C_SDSP 0xe003
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#define INSN_MATCH_C_LWSP 0x4002
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#define INSN_MASK_C_LWSP 0xe003
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#define INSN_MATCH_C_SWSP 0xc002
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#define INSN_MASK_C_SWSP 0xe003
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#define INSN_MATCH_C_FLD 0x2000
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#define INSN_MASK_C_FLD 0xe003
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#define INSN_MATCH_C_FLW 0x6000
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#define INSN_MASK_C_FLW 0xe003
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#define INSN_MATCH_C_FSD 0xa000
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#define INSN_MASK_C_FSD 0xe003
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#define INSN_MATCH_C_FSW 0xe000
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#define INSN_MASK_C_FSW 0xe003
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#define INSN_MATCH_C_FLDSP 0x2002
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#define INSN_MASK_C_FLDSP 0xe003
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#define INSN_MATCH_C_FSDSP 0xa002
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#define INSN_MASK_C_FSDSP 0xe003
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#define INSN_MATCH_C_FLWSP 0x6002
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#define INSN_MASK_C_FLWSP 0xe003
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#define INSN_MATCH_C_FSWSP 0xe002
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#define INSN_MASK_C_FSWSP 0xe003
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#define INSN_LEN(insn) ((((insn) & 0x3) < 0x3) ? 2 : 4)
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#if __riscv_xlen == 64
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#define LOG_REGBYTES 3
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#else
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#define LOG_REGBYTES 2
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#endif
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#define REGBYTES (1 << LOG_REGBYTES)
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#define SH_RD 7
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#define SH_RS1 15
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#define SH_RS2 20
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#define SH_RS2C 2
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#define RV_X(x, s, n) (((x) >> (s)) & ((1 << (n)) - 1))
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#define RVC_LW_IMM(x) ((RV_X(x, 6, 1) << 2) | \
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(RV_X(x, 10, 3) << 3) | \
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(RV_X(x, 5, 1) << 6))
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#define RVC_LD_IMM(x) ((RV_X(x, 10, 3) << 3) | \
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(RV_X(x, 5, 2) << 6))
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#define RVC_LWSP_IMM(x) ((RV_X(x, 4, 3) << 2) | \
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(RV_X(x, 12, 1) << 5) | \
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(RV_X(x, 2, 2) << 6))
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#define RVC_LDSP_IMM(x) ((RV_X(x, 5, 2) << 3) | \
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(RV_X(x, 12, 1) << 5) | \
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(RV_X(x, 2, 3) << 6))
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#define RVC_SWSP_IMM(x) ((RV_X(x, 9, 4) << 2) | \
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(RV_X(x, 7, 2) << 6))
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#define RVC_SDSP_IMM(x) ((RV_X(x, 10, 3) << 3) | \
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(RV_X(x, 7, 3) << 6))
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#define RVC_RS1S(insn) (8 + RV_X(insn, SH_RD, 3))
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#define RVC_RS2S(insn) (8 + RV_X(insn, SH_RS2C, 3))
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#define RVC_RS2(insn) RV_X(insn, SH_RS2C, 5)
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#define SHIFT_RIGHT(x, y) \
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((y) < 0 ? ((x) << -(y)) : ((x) >> (y)))
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#define REG_MASK \
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((1 << (5 + LOG_REGBYTES)) - (1 << LOG_REGBYTES))
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#define REG_OFFSET(insn, pos) \
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(SHIFT_RIGHT((insn), (pos) - LOG_REGBYTES) & REG_MASK)
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#define REG_PTR(insn, pos, regs) \
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(ulong *)((ulong)(regs) + REG_OFFSET(insn, pos))
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#define GET_RM(insn) (((insn) >> 12) & 7)
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#define GET_RS1(insn, regs) (*REG_PTR(insn, SH_RS1, regs))
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#define GET_RS2(insn, regs) (*REG_PTR(insn, SH_RS2, regs))
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#define GET_RS1S(insn, regs) (*REG_PTR(RVC_RS1S(insn), 0, regs))
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#define GET_RS2S(insn, regs) (*REG_PTR(RVC_RS2S(insn), 0, regs))
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#define GET_RS2C(insn, regs) (*REG_PTR(insn, SH_RS2C, regs))
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#define GET_SP(regs) (*REG_PTR(2, 0, regs))
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#define SET_RD(insn, regs, val) (*REG_PTR(insn, SH_RD, regs) = (val))
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#define IMM_I(insn) ((s32)(insn) >> 20)
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#define IMM_S(insn) (((s32)(insn) >> 25 << 5) | \
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(s32)(((insn) >> 7) & 0x1f))
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#define MASK_FUNCT3 0x7000
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#endif
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@ -26,19 +26,4 @@
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#define STR(x) XSTR(x)
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#define XSTR(x) #x
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#if __riscv_xlen == 64
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#define SLL32 sllw
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#define STORE sd
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#define LOAD ld
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#define LWU lwu
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#define LOG_REGBYTES 3
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#else
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#define SLL32 sll
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#define STORE sw
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#define LOAD lw
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#define LWU lw
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#define LOG_REGBYTES 2
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#endif
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#define REGBYTES (1 << LOG_REGBYTES)
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#endif
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@ -16,56 +16,6 @@
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#include <sbi/sbi_trap.h>
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#include <sbi/sbi_unpriv.h>
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#define SH_RD 7
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#define SH_RS1 15
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#define SH_RS2 20
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#define SH_RS2C 2
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#define RV_X(x, s, n) (((x) >> (s)) & ((1 << (n)) - 1))
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#define RVC_LW_IMM(x) ((RV_X(x, 6, 1) << 2) | \
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(RV_X(x, 10, 3) << 3) | \
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(RV_X(x, 5, 1) << 6))
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#define RVC_LD_IMM(x) ((RV_X(x, 10, 3) << 3) | \
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(RV_X(x, 5, 2) << 6))
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#define RVC_LWSP_IMM(x) ((RV_X(x, 4, 3) << 2) | \
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(RV_X(x, 12, 1) << 5) | \
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(RV_X(x, 2, 2) << 6))
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#define RVC_LDSP_IMM(x) ((RV_X(x, 5, 2) << 3) | \
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(RV_X(x, 12, 1) << 5) | \
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(RV_X(x, 2, 3) << 6))
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#define RVC_SWSP_IMM(x) ((RV_X(x, 9, 4) << 2) | \
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(RV_X(x, 7, 2) << 6))
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#define RVC_SDSP_IMM(x) ((RV_X(x, 10, 3) << 3) | \
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(RV_X(x, 7, 3) << 6))
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#define RVC_RS1S(insn) (8 + RV_X(insn, SH_RD, 3))
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#define RVC_RS2S(insn) (8 + RV_X(insn, SH_RS2C, 3))
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#define RVC_RS2(insn) RV_X(insn, SH_RS2C, 5)
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#define SHIFT_RIGHT(x, y) ((y) < 0 ? ((x) << -(y)) : ((x) >> (y)))
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#define REG_MASK \
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((1 << (5 + LOG_REGBYTES)) - (1 << LOG_REGBYTES))
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#define REG_OFFSET(insn, pos) \
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(SHIFT_RIGHT((insn), (pos) - LOG_REGBYTES) & REG_MASK)
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#define REG_PTR(insn, pos, regs)\
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(ulong *)((ulong)(regs) + REG_OFFSET(insn, pos))
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#define GET_RM(insn) (((insn) >> 12) & 7)
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#define GET_RS1(insn, regs) (*REG_PTR(insn, SH_RS1, regs))
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#define GET_RS2(insn, regs) (*REG_PTR(insn, SH_RS2, regs))
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#define GET_RS1S(insn, regs) (*REG_PTR(RVC_RS1S(insn), 0, regs))
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#define GET_RS2S(insn, regs) (*REG_PTR(RVC_RS2S(insn), 0, regs))
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#define GET_RS2C(insn, regs) (*REG_PTR(insn, SH_RS2C, regs))
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#define GET_SP(regs) (*REG_PTR(2, 0, regs))
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#define SET_RD(insn, regs, val) (*REG_PTR(insn, SH_RD, regs) = (val))
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#define IMM_I(insn) ((s32)(insn) >> 20)
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#define IMM_S(insn) (((s32)(insn) >> 25 << 5) | \
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(s32)(((insn) >> 7) & 0x1f))
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#define MASK_FUNCT3 0x7000
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typedef int (*illegal_insn_func)(ulong insn,
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u32 hartid, ulong mcause,
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struct sbi_trap_regs *regs,
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