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lib: provide a platform specific tlb range flush threshold
Currently, the tlb range flush threshold is fixed and set to 4k for all platforms. However, it should be platform specific as it completely depends upon how platform actually implements sfence instruction. Define a platform feature that allows every individual platform to set different values. If a platform doesn't define it, just use a page size as the threshold. Signed-off-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
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4 changed files with 29 additions and 4 deletions
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@ -30,10 +30,14 @@
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#define SBI_PLATFORM_HART_STACK_SIZE_OFFSET (0x54)
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/** Offset of disabled_hart_mask in struct sbi_platform */
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#define SBI_PLATFORM_DISABLED_HART_OFFSET (0x58)
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/** Offset of tlb_range_flush_limit in struct sbi_platform */
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#define SBI_PLATFORM_TLB_RANGE_FLUSH_LIMIT_OFFSET (0x60)
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/** Offset of platform_ops_addr in struct sbi_platform */
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#define SBI_PLATFORM_OPS_OFFSET (0x60)
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#define SBI_PLATFORM_OPS_OFFSET (0x68)
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/** Offset of firmware_context in struct sbi_platform */
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#define SBI_PLATFORM_FIRMWARE_CONTEXT_OFFSET (0x60 + __SIZEOF_POINTER__)
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#define SBI_PLATFORM_FIRMWARE_CONTEXT_OFFSET (0x68 + __SIZEOF_POINTER__)
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#define SBI_PLATFORM_TLB_RANGE_FLUSH_LIMIT_DEFAULT (1UL << 12)
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#ifndef __ASSEMBLY__
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@ -134,6 +138,8 @@ struct sbi_platform {
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u32 hart_stack_size;
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/** Mask representing the set of disabled HARTs */
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u64 disabled_hart_mask;
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/* Maximum value of tlb flush range request*/
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u64 tlb_range_flush_limit;
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/** Pointer to sbi platform operations */
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unsigned long platform_ops_addr;
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/** Pointer to system firmware specific context */
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@ -198,6 +204,22 @@ static inline bool sbi_platform_hart_disabled(const struct sbi_platform *plat,
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return FALSE;
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}
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/**
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* Get platform specific tlb range flush maximum value. Any request with size
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* higher than this is upgraded to a full flush.
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*
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* @param plat pointer to struct sbi_platform
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*
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* @return tlb range flush limit value. Returns a default (page size) if not
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* defined by platform.
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*/
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static inline u64 sbi_platform_tlbr_flush_limit(const struct sbi_platform *plat)
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{
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if (plat)
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return plat->tlb_range_flush_limit;
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return SBI_PLATFORM_TLB_RANGE_FLUSH_LIMIT_DEFAULT;
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}
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/**
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* Get total number of HARTs supported by the platform
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*
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@ -16,7 +16,6 @@
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/* clang-format off */
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#define SBI_TLB_FLUSH_ALL ((unsigned long)-1)
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#define SBI_TLB_FLUSH_MAX_SIZE (1UL << 12)
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/* clang-format on */
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@ -23,6 +23,7 @@
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static unsigned long tlb_sync_off;
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static unsigned long tlb_fifo_off;
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static unsigned long tlb_fifo_mem_off;
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static unsigned long tlb_range_flush_limit;
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static void sbi_tlb_flush_all(void)
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{
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@ -232,7 +233,7 @@ int sbi_tlb_fifo_update(struct sbi_scratch *rscratch, u32 hartid, void *data)
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* upgrade it to flush all because we can only flush
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* 4KB at a time.
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*/
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if (tinfo->size > SBI_TLB_FLUSH_MAX_SIZE) {
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if (tinfo->size > tlb_range_flush_limit) {
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tinfo->start = 0;
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tinfo->size = SBI_TLB_FLUSH_ALL;
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}
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@ -276,6 +277,7 @@ int sbi_tlb_fifo_init(struct sbi_scratch *scratch, bool cold_boot)
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void *tlb_mem;
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unsigned long *tlb_sync;
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struct sbi_fifo *tlb_q;
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const struct sbi_platform *plat = sbi_platform_ptr(scratch);
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if (cold_boot) {
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tlb_sync_off = sbi_scratch_alloc_offset(sizeof(*tlb_sync),
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@ -296,6 +298,7 @@ int sbi_tlb_fifo_init(struct sbi_scratch *scratch, bool cold_boot)
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sbi_scratch_free_offset(tlb_sync_off);
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return SBI_ENOMEM;
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}
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tlb_range_flush_limit = sbi_platform_tlbr_flush_limit(plat);
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} else {
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if (!tlb_sync_off ||
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!tlb_fifo_off ||
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@ -224,5 +224,6 @@ const struct sbi_platform platform = {
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.hart_count = 1,
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.hart_stack_size = 4096,
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.disabled_hart_mask = 0,
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.tlb_range_flush_limit = 0,
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.platform_ops_addr = (unsigned long)&platform_ops
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};
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