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Initial commit.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
This commit is contained in:
Anup Patel
Anup Patel
commit
9e8ff05cb6
67 changed files with 6084 additions and 0 deletions
244
include/sbi/riscv_asm.h
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244
include/sbi/riscv_asm.h
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/*
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* Copyright (c) 2018 Western Digital Corporation or its affiliates.
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*
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* Authors:
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* Anup Patel <anup.patel@wdc.com>
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*
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* SPDX-License-Identifier: BSD-2-Clause
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*/
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#ifndef __RISCV_ASM_H__
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#define __RISCV_ASM_H__
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#ifdef __ASSEMBLY__
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#define __ASM_STR(x) x
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#else
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#define __ASM_STR(x) #x
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#endif
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#if __riscv_xlen == 64
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#define __REG_SEL(a, b) __ASM_STR(a)
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#elif __riscv_xlen == 32
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#define __REG_SEL(a, b) __ASM_STR(b)
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#else
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#error "Unexpected __riscv_xlen"
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#endif
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#define REG_L __REG_SEL(ld, lw)
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#define REG_S __REG_SEL(sd, sw)
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#define SZREG __REG_SEL(8, 4)
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#define LGREG __REG_SEL(3, 2)
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#if __SIZEOF_POINTER__ == 8
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#ifdef __ASSEMBLY__
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#define RISCV_PTR .dword
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#define RISCV_SZPTR 8
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#define RISCV_LGPTR 3
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#else
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#define RISCV_PTR ".dword"
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#define RISCV_SZPTR "8"
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#define RISCV_LGPTR "3"
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#endif
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#elif __SIZEOF_POINTER__ == 4
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#ifdef __ASSEMBLY__
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#define RISCV_PTR .word
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#define RISCV_SZPTR 4
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#define RISCV_LGPTR 2
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#else
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#define RISCV_PTR ".word"
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#define RISCV_SZPTR "4"
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#define RISCV_LGPTR "2"
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#endif
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#else
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#error "Unexpected __SIZEOF_POINTER__"
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#endif
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#if (__SIZEOF_INT__ == 4)
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#define RISCV_INT __ASM_STR(.word)
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#define RISCV_SZINT __ASM_STR(4)
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#define RISCV_LGINT __ASM_STR(2)
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#else
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#error "Unexpected __SIZEOF_INT__"
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#endif
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#if (__SIZEOF_SHORT__ == 2)
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#define RISCV_SHORT __ASM_STR(.half)
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#define RISCV_SZSHORT __ASM_STR(2)
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#define RISCV_LGSHORT __ASM_STR(1)
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#else
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#error "Unexpected __SIZEOF_SHORT__"
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#endif
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#define RISCV_SCRATCH_TMP0_OFFSET (0 * __SIZEOF_POINTER__)
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#define RISCV_SCRATCH_FW_START_OFFSET (1 * __SIZEOF_POINTER__)
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#define RISCV_SCRATCH_FW_SIZE_OFFSET (2 * __SIZEOF_POINTER__)
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#define RISCV_SCRATCH_NEXT_ARG1_OFFSET (3 * __SIZEOF_POINTER__)
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#define RISCV_SCRATCH_NEXT_ADDR_OFFSET (4 * __SIZEOF_POINTER__)
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#define RISCV_SCRATCH_NEXT_MODE_OFFSET (5 * __SIZEOF_POINTER__)
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#define RISCV_SCRATCH_WARMBOOT_ADDR_OFFSET (6 * __SIZEOF_POINTER__)
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#define RISCV_SCRATCH_PLATFORM_ADDR_OFFSET (7 * __SIZEOF_POINTER__)
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#define RISCV_SCRATCH_HARTID_TO_SCRATCH_OFFSET (8 * __SIZEOF_POINTER__)
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#define RISCV_SCRATCH_IPI_TYPE_OFFSET (9 * __SIZEOF_POINTER__)
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#define RISCV_SCRATCH_SIZE 256
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#define RISCV_TRAP_REGS_zero 0
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#define RISCV_TRAP_REGS_ra 1
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#define RISCV_TRAP_REGS_sp 2
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#define RISCV_TRAP_REGS_gp 3
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#define RISCV_TRAP_REGS_tp 4
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#define RISCV_TRAP_REGS_t0 5
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#define RISCV_TRAP_REGS_t1 6
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#define RISCV_TRAP_REGS_t2 7
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#define RISCV_TRAP_REGS_s0 8
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#define RISCV_TRAP_REGS_s1 9
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#define RISCV_TRAP_REGS_a0 10
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#define RISCV_TRAP_REGS_a1 11
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#define RISCV_TRAP_REGS_a2 12
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#define RISCV_TRAP_REGS_a3 13
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#define RISCV_TRAP_REGS_a4 14
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#define RISCV_TRAP_REGS_a5 15
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#define RISCV_TRAP_REGS_a6 16
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#define RISCV_TRAP_REGS_a7 17
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#define RISCV_TRAP_REGS_s2 18
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#define RISCV_TRAP_REGS_s3 19
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#define RISCV_TRAP_REGS_s4 20
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#define RISCV_TRAP_REGS_s5 21
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#define RISCV_TRAP_REGS_s6 22
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#define RISCV_TRAP_REGS_s7 23
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#define RISCV_TRAP_REGS_s8 24
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#define RISCV_TRAP_REGS_s9 25
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#define RISCV_TRAP_REGS_s10 26
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#define RISCV_TRAP_REGS_s11 27
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#define RISCV_TRAP_REGS_t3 28
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#define RISCV_TRAP_REGS_t4 29
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#define RISCV_TRAP_REGS_t5 30
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#define RISCV_TRAP_REGS_t6 31
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#define RISCV_TRAP_REGS_mepc 32
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#define RISCV_TRAP_REGS_mstatus 33
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#define RISCV_TRAP_REGS_last 34
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#define RISCV_TRAP_REGS_OFFSET(x) \
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((RISCV_TRAP_REGS_##x) * __SIZEOF_POINTER__)
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#define RISCV_TRAP_REGS_SIZE RISCV_TRAP_REGS_OFFSET(last)
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#ifndef __ASSEMBLY__
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#define csr_swap(csr, val) \
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({ \
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unsigned long __v = (unsigned long)(val); \
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__asm__ __volatile__ ("csrrw %0, " #csr ", %1" \
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: "=r" (__v) : "rK" (__v) \
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: "memory"); \
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__v; \
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})
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#define csr_read(csr) \
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({ \
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register unsigned long __v; \
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__asm__ __volatile__ ("csrr %0, " #csr \
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: "=r" (__v) : \
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: "memory"); \
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__v; \
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})
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#define csr_read_n(csr_num) \
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({ \
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register unsigned long __v; \
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__asm__ __volatile__ ("csrr %0, " __ASM_STR(csr_num) \
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: "=r" (__v) : \
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: "memory"); \
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__v; \
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})
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#define csr_write(csr, val) \
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({ \
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unsigned long __v = (unsigned long)(val); \
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__asm__ __volatile__ ("csrw " #csr ", %0" \
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: : "rK" (__v) \
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: "memory"); \
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})
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#define csr_write_n(csr_num, val) \
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({ \
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unsigned long __v = (unsigned long)(val); \
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__asm__ __volatile__ ("csrw " __ASM_STR(csr_num) ", %0" \
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: : "rK" (__v) \
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: "memory"); \
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})
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#define csr_read_set(csr, val) \
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({ \
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unsigned long __v = (unsigned long)(val); \
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__asm__ __volatile__ ("csrrs %0, " #csr ", %1" \
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: "=r" (__v) : "rK" (__v) \
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: "memory"); \
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__v; \
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})
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#define csr_set(csr, val) \
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({ \
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unsigned long __v = (unsigned long)(val); \
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__asm__ __volatile__ ("csrs " #csr ", %0" \
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: : "rK" (__v) \
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: "memory"); \
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})
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#define csr_read_clear(csr, val) \
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({ \
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unsigned long __v = (unsigned long)(val); \
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__asm__ __volatile__ ("csrrc %0, " #csr ", %1" \
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: "=r" (__v) : "rK" (__v) \
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: "memory"); \
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__v; \
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})
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#define csr_clear(csr, val) \
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({ \
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unsigned long __v = (unsigned long)(val); \
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__asm__ __volatile__ ("csrc " #csr ", %0" \
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: : "rK" (__v) \
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: "memory"); \
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})
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unsigned long csr_read_num(int csr_num);
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void csr_write_num(int csr_num, unsigned long val);
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#define wfi() \
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do { \
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__asm__ __volatile__ ("wfi" ::: "memory"); \
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} while (0)
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static inline int misa_extension(char ext)
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{
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return csr_read(misa) & (1 << (ext - 'A'));
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}
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static inline int misa_xlen(void)
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{
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return ((long)csr_read(misa) < 0) ? 64 : 32;
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}
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static inline void misa_string(char *out, unsigned int out_sz)
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{
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unsigned long i, val = csr_read(misa);
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for (i = 0; i < 26; i++) {
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if (val & (1 << i)) {
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*out = 'A' + i;
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out++;
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}
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}
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*out = '\0';
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out++;
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}
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int pmp_set(unsigned int n, unsigned long prot,
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unsigned long addr, unsigned long log2len);
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int pmp_get(unsigned int n, unsigned long *prot_out,
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unsigned long *addr_out, unsigned long *log2len_out);
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#endif /* !__ASSEMBLY__ */
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#endif
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