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sbi: sbi_pmu: Add hw_counter_filter_mode() to pmu device
Add support for custom PMU extensions to set inhibit bits on custom CSRs by introducing the PMU device callback hw_counter_filter_mode(). This allows the perf tool to restrict event counting under a specified privileged mode by appending a modifier, e.g. perf record -e event:k to count events only happening in kernel mode. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Atish Patra <atishp@rivosinc.com> Reviewed-by: Anup Patel <anup@brainfault.org>
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090fa99d7c
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2 changed files with 20 additions and 6 deletions
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@ -89,6 +89,12 @@ struct sbi_pmu_device {
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* Custom function returning the machine-specific irq-bit.
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*/
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int (*hw_counter_irq_bit)(void);
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/**
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* Custom function to inhibit counting of events while in
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* specified mode.
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*/
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void (*hw_counter_filter_mode)(unsigned long flags, int counter_index);
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};
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/** Get the PMU platform device */
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@ -599,7 +599,10 @@ static int pmu_update_hw_mhpmevent(struct sbi_pmu_hw_event *hw_evt, int ctr_idx,
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pmu_dev->hw_counter_disable_irq(ctr_idx);
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/* Update the inhibit flags based on inhibit flags received from supervisor */
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pmu_update_inhibit_flags(flags, &mhpmevent_val);
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if (sbi_hart_has_extension(scratch, SBI_HART_EXT_SSCOFPMF))
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pmu_update_inhibit_flags(flags, &mhpmevent_val);
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if (pmu_dev && pmu_dev->hw_counter_filter_mode)
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pmu_dev->hw_counter_filter_mode(flags, ctr_idx);
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#if __riscv_xlen == 32
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csr_write_num(CSR_MHPMEVENT3 + ctr_idx - 3, mhpmevent_val & 0xFFFFFFFF);
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@ -620,7 +623,8 @@ static int pmu_fixed_ctr_update_inhibit_bits(int fixed_ctr, unsigned long flags)
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#if __riscv_xlen == 32
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uint64_t cfgh_csr_no;
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#endif
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if (!sbi_hart_has_extension(scratch, SBI_HART_EXT_SMCNTRPMF))
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if (!sbi_hart_has_extension(scratch, SBI_HART_EXT_SMCNTRPMF) &&
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!(pmu_dev && pmu_dev->hw_counter_filter_mode))
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return fixed_ctr;
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switch (fixed_ctr) {
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@ -641,13 +645,17 @@ static int pmu_fixed_ctr_update_inhibit_bits(int fixed_ctr, unsigned long flags)
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}
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cfg_val |= MHPMEVENT_MINH;
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pmu_update_inhibit_flags(flags, &cfg_val);
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if (sbi_hart_has_extension(scratch, SBI_HART_EXT_SMCNTRPMF)) {
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pmu_update_inhibit_flags(flags, &cfg_val);
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#if __riscv_xlen == 32
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csr_write_num(cfg_csr_no, cfg_val & 0xFFFFFFFF);
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csr_write_num(cfgh_csr_no, cfg_val >> BITS_PER_LONG);
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csr_write_num(cfg_csr_no, cfg_val & 0xFFFFFFFF);
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csr_write_num(cfgh_csr_no, cfg_val >> BITS_PER_LONG);
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#else
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csr_write_num(cfg_csr_no, cfg_val);
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csr_write_num(cfg_csr_no, cfg_val);
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#endif
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}
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if (pmu_dev && pmu_dev->hw_counter_filter_mode)
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pmu_dev->hw_counter_filter_mode(flags, fixed_ctr);
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return fixed_ctr;
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}
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