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https://github.com/Fishwaldo/opensbi.git
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platform: fu540: Initial commit of Microsemi device tree
Add a device tree for th HiFive Unleashed that includes the Microsemi PCIe root complex. Once we have support for u-boot and in tree Linux kernel device trees this device tree should be removed. Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Alistair Francis
Anup Patel
parent
afbb0cdf80
commit
ae4e0de700
1 changed files with 588 additions and 0 deletions
588
platform/sifive/fu540/HiFiveUnleashed-MicroSemi-Expansion.dts
Normal file
588
platform/sifive/fu540/HiFiveUnleashed-MicroSemi-Expansion.dts
Normal file
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@ -0,0 +1,588 @@
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/dts-v1/;
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/ {
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#address-cells = <0x2>;
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#size-cells = <0x2>;
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compatible = "sifive,fu540g", "sifive,fu500";
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model = "sifive,hifive-unleashed-a00";
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aliases {
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serial0 = "/soc/serial@10010000";
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serial1 = "/soc/serial@10011000";
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};
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chosen {
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stdout-path = "/soc/serial@10010000:115200";
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};
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firmware {
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sifive,fsbl = "2018-03-20";
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};
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cpus {
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#address-cells = <0x1>;
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#size-cells = <0x0>;
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timebase-frequency = <0xf4240>;
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cpu@0 {
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clock-frequency = <0x0>;
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compatible = "sifive,rocket0", "riscv";
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device_type = "cpu";
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i-cache-block-size = <0x40>;
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i-cache-sets = <0x80>;
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i-cache-size = <0x4000>;
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next-level-cache = <0x1 0x2>;
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reg = <0x0>;
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riscv,isa = "rv64imac";
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sifive,dtim = <0x3>;
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sifive,itim = <0x4>;
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status = "masked";
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interrupt-controller {
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#interrupt-cells = <0x1>;
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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linux,phandle = <0xf>;
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phandle = <0xf>;
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};
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};
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cpu@1 {
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clock-frequency = <0x0>;
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compatible = "sifive,rocket0", "riscv";
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d-cache-block-size = <0x40>;
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d-cache-sets = <0x40>;
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d-cache-size = <0x8000>;
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d-tlb-sets = <0x1>;
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d-tlb-size = <0x20>;
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device_type = "cpu";
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i-cache-block-size = <0x40>;
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i-cache-sets = <0x40>;
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i-cache-size = <0x8000>;
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i-tlb-sets = <0x1>;
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i-tlb-size = <0x20>;
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mmu-type = "riscv,sv39";
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next-level-cache = <0x1 0x2>;
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reg = <0x1>;
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riscv,isa = "rv64imafdc";
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sifive,itim = <0x5>;
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status = "okay";
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tlb-split;
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interrupt-controller {
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#interrupt-cells = <0x1>;
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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linux,phandle = <0x10>;
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phandle = <0x10>;
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};
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};
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cpu@2 {
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clock-frequency = <0x0>;
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compatible = "sifive,rocket0", "riscv";
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d-cache-block-size = <0x40>;
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d-cache-sets = <0x40>;
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d-cache-size = <0x8000>;
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d-tlb-sets = <0x1>;
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d-tlb-size = <0x20>;
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device_type = "cpu";
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i-cache-block-size = <0x40>;
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i-cache-sets = <0x40>;
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i-cache-size = <0x8000>;
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i-tlb-sets = <0x1>;
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i-tlb-size = <0x20>;
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mmu-type = "riscv,sv39";
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next-level-cache = <0x1 0x2>;
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reg = <0x2>;
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riscv,isa = "rv64imafdc";
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sifive,itim = <0x6>;
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status = "okay";
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tlb-split;
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interrupt-controller {
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#interrupt-cells = <0x1>;
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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linux,phandle = <0x11>;
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phandle = <0x11>;
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};
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};
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cpu@3 {
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clock-frequency = <0x0>;
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compatible = "sifive,rocket0", "riscv";
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d-cache-block-size = <0x40>;
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d-cache-sets = <0x40>;
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d-cache-size = <0x8000>;
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d-tlb-sets = <0x1>;
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d-tlb-size = <0x20>;
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device_type = "cpu";
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i-cache-block-size = <0x40>;
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i-cache-sets = <0x40>;
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i-cache-size = <0x8000>;
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i-tlb-sets = <0x1>;
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i-tlb-size = <0x20>;
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mmu-type = "riscv,sv39";
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next-level-cache = <0x1 0x2>;
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reg = <0x3>;
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riscv,isa = "rv64imafdc";
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sifive,itim = <0x7>;
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status = "okay";
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tlb-split;
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interrupt-controller {
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#interrupt-cells = <0x1>;
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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linux,phandle = <0x12>;
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phandle = <0x12>;
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};
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};
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cpu@4 {
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clock-frequency = <0x0>;
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compatible = "sifive,rocket0", "riscv";
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d-cache-block-size = <0x40>;
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d-cache-sets = <0x40>;
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d-cache-size = <0x8000>;
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d-tlb-sets = <0x1>;
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d-tlb-size = <0x20>;
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device_type = "cpu";
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i-cache-block-size = <0x40>;
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i-cache-sets = <0x40>;
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i-cache-size = <0x8000>;
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i-tlb-sets = <0x1>;
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i-tlb-size = <0x20>;
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mmu-type = "riscv,sv39";
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next-level-cache = <0x1 0x2>;
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reg = <0x4>;
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riscv,isa = "rv64imafdc";
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sifive,itim = <0x8>;
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status = "okay";
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tlb-split;
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interrupt-controller {
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#interrupt-cells = <0x1>;
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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linux,phandle = <0x13>;
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phandle = <0x13>;
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};
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};
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};
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memory@80000000 {
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device_type = "memory";
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reg = <0x0 0x80000000 0x2 0x0>;
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linux,phandle = <0xe>;
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phandle = <0xe>;
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};
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soc {
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#address-cells = <0x2>;
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#size-cells = <0x2>;
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compatible = "SiFive,FU540G-soc", "fu500-soc", "sifive-soc", "simple-bus";
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ranges;
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refclk {
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#clock-cells = <0x0>;
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compatible = "fixed-clock";
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clock-frequency = <0x1fca055>;
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clock-output-names = "xtal";
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linux,phandle = <0x9>;
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phandle = <0x9>;
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};
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prci@10000000 {
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compatible = "sifive,aloeprci0";
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reg = <0x0 0x10000000 0x0 0x1000>;
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reg-names = "control";
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clocks = <0x9>;
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#clock-cells = <0x1>;
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linux,phandle = <0xa>;
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phandle = <0xa>;
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};
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tlclk {
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compatible = "fixed-factor-clock";
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clocks = <0xa 0x0>;
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#clock-cells = <0x0>;
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clock-div = <0x2>;
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clock-mult = <0x1>;
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linux,phandle = <0x16>;
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phandle = <0x16>;
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};
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cadence-gemgxl-mgmt@100a0000 {
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compatible = "sifive,cadencegemgxlmgmt0";
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reg = <0x0 0x100a0000 0x0 0x1000>;
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reg-names = "control";
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#clock-cells = <0x0>;
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linux,phandle = <0x14>;
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phandle = <0x14>;
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};
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bus-blocker@100b8000 {
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compatible = "sifive,bus-blocker0";
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reg = <0x0 0x100b8000 0x0 0x1000>;
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reg-names = "control";
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};
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cache-controller@2010000 {
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cache-block-size = <0x40>;
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cache-level = <0x2>;
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cache-sets = <0x800>;
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cache-size = <0x200000>;
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cache-unified;
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compatible = "sifive,ccache0", "cache";
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interrupt-parent = <0xb>;
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interrupts = <0x1 0x2 0x3>;
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next-level-cache = <0xc 0xd 0xe>;
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reg = <0x0 0x2010000 0x0 0x1000 0x0 0x8000000 0x0 0x2000000>;
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reg-names = "control", "sideband";
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linux,phandle = <0x2>;
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phandle = <0x2>;
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};
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cadence-ddr-mgmt@100c0000 {
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compatible = "sifive,cadenceddrmgmt0";
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reg = <0x0 0x100c0000 0x0 0x1000>;
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reg-names = "control";
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};
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chiplink@40000000 {
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#address-cells = <0x2>;
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#size-cells = <0x2>;
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compatible = "sifive,chiplink", "simple-bus";
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ranges = <0x0 0x60000000 0x0 0x60000000 0x0 0x20000000 0x30 0x0 0x30 0x0 0x10 0x0 0x0 0x40000000 0x0 0x40000000 0x0 0x20000000 0x20 0x0 0x20 0x0 0x10 0x0>;
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linux,phandle = <0xd>;
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phandle = <0xd>;
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};
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dma@3000000 {
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#dma-cells = <0x1>;
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compatible = "riscv,dma0";
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dma-channels = <0x4>;
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dma-requests = <0x0>;
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interrupt-parent = <0xb>;
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interrupts = <0x17 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e>;
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reg = <0x0 0x3000000 0x0 0x100000>;
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reg-names = "control";
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riscv,dma-pools = <0x1>;
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};
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dtim@1000000 {
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compatible = "sifive,dtim0";
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reg = <0x0 0x1000000 0x0 0x2000>;
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reg-names = "mem";
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linux,phandle = <0x3>;
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phandle = <0x3>;
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};
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ememoryotp@10070000 {
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compatible = "sifive,ememoryotp0";
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reg = <0x0 0x10070000 0x0 0x1000>;
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reg-names = "control";
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};
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error-device@18000000 {
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compatible = "sifive,error0";
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reg = <0x0 0x18000000 0x0 0x8000000>;
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reg-names = "mem";
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linux,phandle = <0x1>;
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phandle = <0x1>;
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};
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ethernet@10090000 {
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compatible = "cdns,macb";
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interrupt-parent = <0xb>;
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interrupts = <0x35>;
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reg = <0x0 0x10090000 0x0 0x2000>;
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reg-names = "control";
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local-mac-address = [70 b3 d5 92 f0 1f];
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phy-mode = "gmii";
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clock-names = "pclk", "hclk", "tx_clk";
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clocks = <0xa 0x1 0xa 0x1 0x14>;
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#address-cells = <0x1>;
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#size-cells = <0x0>;
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ethernet-phy@0 {
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reg = <0x0>;
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reset-gpios = <0x15 0xc 0x1>;
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};
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};
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gpio@10060000 {
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compatible = "sifive,gpio0";
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interrupt-parent = <0xb>;
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interrupts = <0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf 0x10 0x11 0x12 0x13 0x14 0x15 0x16>;
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reg = <0x0 0x10060000 0x0 0x1000>;
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reg-names = "control";
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gpio-controller;
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#gpio-cells = <0x2>;
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interrupt-controller;
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#interrupt-cells = <0x2>;
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linux,phandle = <0x15>;
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phandle = <0x15>;
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};
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gpio-restart {
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compatible = "gpio-restart";
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gpios = <0x15 0xa 0x1>;
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};
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i2c@10030000 {
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compatible = "sifive,i2c0", "opencores,i2c-ocores";
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reg = <0x0 0x10030000 0x0 0x1000>;
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reg-names = "control";
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clocks = <0x16>;
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reg-shift = <0x2>;
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reg-io-width = <0x1>;
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#address-cells = <0x1>;
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#size-cells = <0x0>;
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};
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interrupt-controller@c000000 {
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#interrupt-cells = <0x1>;
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compatible = "riscv,plic0";
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interrupt-controller;
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interrupts-extended = <0xf 0xffffffff 0x10 0xffffffff 0x10 0x9 0x11 0xffffffff 0x11 0x9 0x12 0xffffffff 0x12 0x9 0x13 0xffffffff 0x13 0x9>;
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reg = <0x0 0xc000000 0x0 0x4000000>;
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reg-names = "control";
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riscv,max-priority = <0x7>;
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riscv,ndev = <0x35>;
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linux,phandle = <0xb>;
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phandle = <0xb>;
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};
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itim@1800000 {
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compatible = "sifive,itim0";
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reg = <0x0 0x1800000 0x0 0x4000>;
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reg-names = "mem";
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linux,phandle = <0x4>;
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phandle = <0x4>;
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};
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itim@1808000 {
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compatible = "sifive,itim0";
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reg = <0x0 0x1808000 0x0 0x8000>;
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reg-names = "mem";
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linux,phandle = <0x5>;
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phandle = <0x5>;
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};
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itim@1810000 {
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compatible = "sifive,itim0";
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reg = <0x0 0x1810000 0x0 0x8000>;
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reg-names = "mem";
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linux,phandle = <0x6>;
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phandle = <0x6>;
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};
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itim@1818000 {
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compatible = "sifive,itim0";
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reg = <0x0 0x1818000 0x0 0x8000>;
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reg-names = "mem";
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linux,phandle = <0x7>;
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phandle = <0x7>;
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};
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itim@1820000 {
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compatible = "sifive,itim0";
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reg = <0x0 0x1820000 0x0 0x8000>;
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reg-names = "mem";
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||||
linux,phandle = <0x8>;
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phandle = <0x8>;
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||||
};
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||||
|
||||
memory-controller@100b0000 {
|
||||
compatible = "sifive,aloeddr0";
|
||||
interrupt-parent = <0xb>;
|
||||
interrupts = <0x1f>;
|
||||
reg = <0x0 0x100b0000 0x0 0x4000>;
|
||||
reg-names = "control";
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||||
};
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||||
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||||
pci@2000000000 {
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||||
#address-cells = <0x3>;
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#interrupt-cells = <0x1>;
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||||
#size-cells = <0x2>;
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||||
compatible = "ms-pf,axi-pcie-host";
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device_type = "pci";
|
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bus-range = <0x01 0x7f>;
|
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interrupt-map = < 0 0 0 1 0x17 1
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0 0 0 2 0x17 2
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0 0 0 3 0x17 3
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0 0 0 4 0x17 4>;
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interrupt-map-mask = <0x0 0x0 0x0 0x7>;
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interrupt-parent = <0xb>;
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interrupts = <0x20>;
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ranges = <0x2000000 0x0 0x40000000 0x0 0x40000000 0x0 0x20000000>;
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reg = < 0x20 0x30000000 0x0 0x4000000
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0x20 0x0 0x0 0x100000 >;
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||||
reg-names = "control", "apb";
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||||
|
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ms_pcie_intc {
|
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#address-cells = <0x0>;
|
||||
#interrupt-cells = <0x1>;
|
||||
interrupt-controller;
|
||||
linux,phandle = <0x17>;
|
||||
phandle = <0x17>;
|
||||
};
|
||||
};
|
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|
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pinctrl@10080000 {
|
||||
compatible = "sifive,pinctrl0";
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reg = <0x0 0x10080000 0x0 0x1000>;
|
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reg-names = "control";
|
||||
};
|
||||
|
||||
pwm@10020000 {
|
||||
compatible = "sifive,pwm0";
|
||||
interrupt-parent = <0xb>;
|
||||
interrupts = <0x2a 0x2b 0x2c 0x2d>;
|
||||
reg = <0x0 0x10020000 0x0 0x1000>;
|
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reg-names = "control";
|
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clocks = <0x16>;
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sifive,approx-period = <0xf4240>;
|
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#pwm-cells = <0x2>;
|
||||
linux,phandle = <0x18>;
|
||||
phandle = <0x18>;
|
||||
};
|
||||
|
||||
pwm@10021000 {
|
||||
compatible = "sifive,pwm0";
|
||||
interrupt-parent = <0xb>;
|
||||
interrupts = <0x2e 0x2f 0x30 0x31>;
|
||||
reg = <0x0 0x10021000 0x0 0x1000>;
|
||||
reg-names = "control";
|
||||
clocks = <0x16>;
|
||||
sifive,approx-period = <0xf4240>;
|
||||
#pwm-cells = <0x2>;
|
||||
};
|
||||
|
||||
pwmleds {
|
||||
compatible = "pwm-leds";
|
||||
|
||||
heartbeat {
|
||||
pwms = <0x18 0x0 0x0>;
|
||||
max-brightness = <0xff>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
|
||||
mtd {
|
||||
pwms = <0x18 0x1 0x0>;
|
||||
max-brightness = <0xff>;
|
||||
linux,default-trigger = "mtd";
|
||||
};
|
||||
|
||||
netdev {
|
||||
pwms = <0x18 0x2 0x0>;
|
||||
max-brightness = <0xff>;
|
||||
linux,default-trigger = "netdev";
|
||||
};
|
||||
|
||||
panic {
|
||||
pwms = <0x18 0x3 0x0>;
|
||||
max-brightness = <0xff>;
|
||||
linux,default-trigger = "panic";
|
||||
};
|
||||
};
|
||||
|
||||
rom@1000 {
|
||||
compatible = "sifive,modeselect0";
|
||||
reg = <0x0 0x1000 0x0 0x1000>;
|
||||
reg-names = "mem";
|
||||
};
|
||||
|
||||
rom@10000 {
|
||||
compatible = "sifive,maskrom0";
|
||||
reg = <0x0 0x10000 0x0 0x8000>;
|
||||
reg-names = "mem";
|
||||
};
|
||||
|
||||
rom@a000000 {
|
||||
compatible = "ucbbar,cacheable-zero0";
|
||||
reg = <0x0 0xa000000 0x0 0x2000000>;
|
||||
reg-names = "mem";
|
||||
linux,phandle = <0xc>;
|
||||
phandle = <0xc>;
|
||||
};
|
||||
|
||||
serial@10010000 {
|
||||
compatible = "sifive,uart0";
|
||||
interrupt-parent = <0xb>;
|
||||
interrupts = <0x4>;
|
||||
reg = <0x0 0x10010000 0x0 0x1000>;
|
||||
reg-names = "control";
|
||||
clocks = <0x16>;
|
||||
};
|
||||
|
||||
serial@10011000 {
|
||||
compatible = "sifive,uart0";
|
||||
interrupt-parent = <0xb>;
|
||||
interrupts = <0x5>;
|
||||
reg = <0x0 0x10011000 0x0 0x1000>;
|
||||
reg-names = "control";
|
||||
clocks = <0x16>;
|
||||
};
|
||||
|
||||
spi@10040000 {
|
||||
compatible = "sifive,spi0";
|
||||
interrupt-parent = <0xb>;
|
||||
interrupts = <0x33>;
|
||||
reg = <0x0 0x10040000 0x0 0x1000 0x0 0x20000000 0x0 0x10000000>;
|
||||
reg-names = "control", "mem";
|
||||
clocks = <0x16>;
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x0>;
|
||||
|
||||
flash@0 {
|
||||
compatible = "issi,is25wp256d", "jedec,spi-nor";
|
||||
reg = <0x0>;
|
||||
spi-max-frequency = <0x2faf080>;
|
||||
m25p,fast-read;
|
||||
spi-tx-bus-width = <0x4>;
|
||||
spi-rx-bus-width = <0x4>;
|
||||
};
|
||||
};
|
||||
|
||||
spi@10041000 {
|
||||
compatible = "sifive,spi0";
|
||||
interrupt-parent = <0xb>;
|
||||
interrupts = <0x34>;
|
||||
reg = <0x0 0x10041000 0x0 0x1000 0x0 0x30000000 0x0 0x10000000>;
|
||||
reg-names = "control", "mem";
|
||||
clocks = <0x16>;
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x0>;
|
||||
};
|
||||
|
||||
spi@10050000 {
|
||||
compatible = "sifive,spi0";
|
||||
interrupt-parent = <0xb>;
|
||||
interrupts = <0x6>;
|
||||
reg = <0x0 0x10050000 0x0 0x1000>;
|
||||
reg-names = "control";
|
||||
clocks = <0x16>;
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x0>;
|
||||
|
||||
mmc@0 {
|
||||
compatible = "mmc-spi-slot";
|
||||
reg = <0x0>;
|
||||
spi-max-frequency = <0x1312d00>;
|
||||
voltage-ranges = <0xce4 0xce4>;
|
||||
disable-wp;
|
||||
gpios = <0x15 0xb 0x1>;
|
||||
};
|
||||
};
|
||||
|
||||
teststatus@4000 {
|
||||
compatible = "sifive,test0";
|
||||
reg = <0x0 0x4000 0x0 0x1000>;
|
||||
reg-names = "control";
|
||||
};
|
||||
};
|
||||
};
|
||||
Loading…
Add table
Add a link
Reference in a new issue