diff --git a/include/sbi/riscv_unpriv.h b/include/sbi/riscv_unpriv.h
index 05aca76..bdea3a3 100644
--- a/include/sbi/riscv_unpriv.h
+++ b/include/sbi/riscv_unpriv.h
@@ -42,7 +42,7 @@ DECLARE_UNPRIVILEGED_LOAD_FUNCTION(u64)
 DECLARE_UNPRIVILEGED_STORE_FUNCTION(u64)
 DECLARE_UNPRIVILEGED_LOAD_FUNCTION(ulong)
 
-ulong get_insn(ulong mepc, bool virt, struct sbi_scratch *scratch,
+ulong get_insn(ulong mepc, struct sbi_scratch *scratch,
 	       struct unpriv_trap *trap);
 
 #endif
diff --git a/lib/sbi/riscv_unpriv.c b/lib/sbi/riscv_unpriv.c
index 4997636..e84c23e 100644
--- a/lib/sbi/riscv_unpriv.c
+++ b/lib/sbi/riscv_unpriv.c
@@ -101,10 +101,10 @@ void store_u64(u64 *addr, u64 val,
 }
 #endif
 
-ulong get_insn(ulong mepc, bool virt, struct sbi_scratch *scratch,
+ulong get_insn(ulong mepc, struct sbi_scratch *scratch,
 	       struct unpriv_trap *trap)
 {
-	ulong __mstatus = 0, __vsstatus = 0, val = 0;
+	ulong __mstatus = 0, val = 0;
 #ifdef __riscv_compressed
 	ulong rvc_mask = 3, tmp;
 #endif
@@ -113,9 +113,6 @@ ulong get_insn(ulong mepc, bool virt, struct sbi_scratch *scratch,
 	trap->tval = 0;
 	sbi_hart_set_trap_info(scratch, trap);
 
-	if (virt)
-		__vsstatus = csr_read_set(CSR_VSSTATUS, SSTATUS_MXR);
-
 #ifndef __riscv_compressed
 	asm("csrrs %[mstatus], " STR(CSR_MSTATUS) ", %[mprv]\n"
 	    ".option push\n"
@@ -149,9 +146,6 @@ ulong get_insn(ulong mepc, bool virt, struct sbi_scratch *scratch,
 	      [rvc_mask] "r"(rvc_mask));
 #endif
 
-	if (virt)
-		csr_write(CSR_VSSTATUS, __vsstatus);
-
 	sbi_hart_set_trap_info(scratch, NULL);
 	switch (trap->cause) {
 	case CAUSE_LOAD_ACCESS:
diff --git a/lib/sbi/sbi_illegal_insn.c b/lib/sbi/sbi_illegal_insn.c
index d15986a..56d51a0 100644
--- a/lib/sbi/sbi_illegal_insn.c
+++ b/lib/sbi/sbi_illegal_insn.c
@@ -130,16 +130,11 @@ int sbi_illegal_insn_handler(u32 hartid, ulong mcause,
 			     struct sbi_scratch *scratch)
 {
 	ulong insn = csr_read(CSR_MTVAL);
-#if __riscv_xlen == 32
-	bool virt = (regs->mstatusH & MSTATUSH_MPV) ? TRUE : FALSE;
-#else
-	bool virt = (regs->mstatus & MSTATUS_MPV) ? TRUE : FALSE;
-#endif
 	struct unpriv_trap uptrap;
 
 	if (unlikely((insn & 3) != 3)) {
 		if (insn == 0) {
-			insn = get_insn(regs->mepc, virt, scratch, &uptrap);
+			insn = get_insn(regs->mepc, scratch, &uptrap);
 			if (uptrap.cause)
 				return sbi_trap_redirect(regs, scratch,
 					regs->mepc, uptrap.cause, uptrap.tval);
diff --git a/lib/sbi/sbi_misaligned_ldst.c b/lib/sbi/sbi_misaligned_ldst.c
index 10c467c..a41b908 100644
--- a/lib/sbi/sbi_misaligned_ldst.c
+++ b/lib/sbi/sbi_misaligned_ldst.c
@@ -29,12 +29,7 @@ int sbi_misaligned_load_handler(u32 hartid, ulong mcause,
 	struct unpriv_trap uptrap;
 	ulong addr = csr_read(CSR_MTVAL);
 	int i, fp = 0, shift = 0, len = 0;
-#if __riscv_xlen == 32
-	bool virt = (regs->mstatusH & MSTATUSH_MPV) ? TRUE : FALSE;
-#else
-	bool virt = (regs->mstatus & MSTATUS_MPV) ? TRUE : FALSE;
-#endif
-	ulong insn = get_insn(regs->mepc, virt, scratch, &uptrap);
+	ulong insn = get_insn(regs->mepc, scratch, &uptrap);
 
 	if (uptrap.cause)
 		return sbi_trap_redirect(regs, scratch, regs->mepc,
@@ -136,12 +131,7 @@ int sbi_misaligned_store_handler(u32 hartid, ulong mcause,
 	struct unpriv_trap uptrap;
 	ulong addr = csr_read(CSR_MTVAL);
 	int i, len = 0;
-#if __riscv_xlen == 32
-	bool virt = (regs->mstatusH & MSTATUSH_MPV) ? TRUE : FALSE;
-#else
-	bool virt = (regs->mstatus & MSTATUS_MPV) ? TRUE : FALSE;
-#endif
-	ulong insn = get_insn(regs->mepc, virt, scratch, &uptrap);
+	ulong insn = get_insn(regs->mepc, scratch, &uptrap);
 
 	if (uptrap.cause)
 		return sbi_trap_redirect(regs, scratch, regs->mepc,