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lib: Extend sbi_trap_redirect() for hypervisor extension
When hypervisor extension is available, we can get traps from VS/VU modes. We should be able to force redirect some of these traps to HS-mode. In other words, we should be able forward traps from VS/VU mode to HS-mode using sbi_trap_redirect() hence this patch. Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Anup Patel
Anup Patel
parent
1a5614e971
commit
bbeb8e619d
4 changed files with 156 additions and 26 deletions
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@ -486,6 +486,16 @@ _trap_handler_all_mode:
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REG_S t0, SBI_TRAP_REGS_OFFSET(mepc)(sp)
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csrr t0, CSR_MSTATUS
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REG_S t0, SBI_TRAP_REGS_OFFSET(mstatus)(sp)
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REG_S zero, SBI_TRAP_REGS_OFFSET(mstatusH)(sp)
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#if __riscv_xlen == 32
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csrr t0, CSR_MISA
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srli t0, t0, ('H' - 'A')
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andi t0, t0, 0x1
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beq t0, zero, _skip_mstatush_save
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csrr t0, CSR_MSTATUSH
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REG_S t0, SBI_TRAP_REGS_OFFSET(mstatusH)(sp)
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_skip_mstatush_save:
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#endif
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/* Save all general regisers except SP and T0 */
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REG_S zero, SBI_TRAP_REGS_OFFSET(zero)(sp)
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@ -560,6 +570,15 @@ _trap_handler_all_mode:
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csrw CSR_MEPC, t0
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REG_L t0, SBI_TRAP_REGS_OFFSET(mstatus)(sp)
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csrw CSR_MSTATUS, t0
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#if __riscv_xlen == 32
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csrr t0, CSR_MISA
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srli t0, t0, ('H' - 'A')
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andi t0, t0, 0x1
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beq t0, zero, _skip_mstatush_restore
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REG_L t0, SBI_TRAP_REGS_OFFSET(mstatusH)(sp)
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csrw CSR_MSTATUSH, t0
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_skip_mstatush_restore:
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#endif
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/* Restore T0 */
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REG_L t0, SBI_TRAP_REGS_OFFSET(t0)(sp)
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@ -58,8 +58,10 @@
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#define SSTATUS_UIE 0x00000001
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#define SSTATUS_SIE 0x00000002
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#define SSTATUS_UPIE 0x00000010
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#define SSTATUS_SPIE 0x00000020
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#define SSTATUS_SPP 0x00000100
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#define SSTATUS_SPIE_SHIFT 5
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#define SSTATUS_SPIE (1UL << MSTATUS_SPIE_SHIFT)
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#define SSTATUS_SPP_SHIFT 8
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#define SSTATUS_SPP (1UL << MSTATUS_SPP_SHIFT)
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#define SSTATUS_FS 0x00006000
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#define SSTATUS_XS 0x00018000
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#define SSTATUS_SUM 0x00040000
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@ -68,6 +70,14 @@
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#define SSTATUS_UXL 0x0000000300000000
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#define SSTATUS64_SD 0x8000000000000000
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#define HSTATUS_VTSR 0x00400000
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#define HSTATUS_VTVM 0x00100000
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#define HSTATUS_SP2V 0x00000200
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#define HSTATUS_SP2P 0x00000100
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#define HSTATUS_SPV 0x00000080
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#define HSTATUS_STL 0x00000040
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#define HSTATUS_SPRV 0x00000001
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#define DCSR_XDEBUGVER (3U<<30)
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#define DCSR_NDRESET (1<<29)
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#define DCSR_FULLRESET (1<<28)
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@ -262,6 +272,23 @@
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#define CSR_STVAL 0x143
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#define CSR_SIP 0x144
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#define CSR_SATP 0x180
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#define CSR_HSTATUS 0x600
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#define CSR_HEDELEG 0x602
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#define CSR_HIDELEG 0x603
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#define CSR_HCOUNTERNEN 0x606
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#define CSR_HGATP 0x680
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#define CSR_VSSTATUS 0x200
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#define CSR_VSIE 0x204
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#define CSR_VSTVEC 0x205
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#define CSR_VSSCRATCH 0x240
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#define CSR_VSEPC 0x241
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#define CSR_VSCAUSE 0x242
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#define CSR_VSTVAL 0x243
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#define CSR_VSIP 0x244
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#define CSR_VSATP 0x280
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#define CSR_MSTATUS 0x300
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#define CSR_MISA 0x301
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#define CSR_MEDELEG 0x302
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@ -302,6 +329,7 @@
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#define CSR_DCSR 0x7b0
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#define CSR_DPC 0x7b1
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#define CSR_DSCRATCH 0x7b2
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#define CSR_MCYCLE 0xb00
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#define CSR_MINSTRET 0xb02
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#define CSR_MHPMCOUNTER3 0xb03
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@ -80,8 +80,10 @@
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#define SBI_TRAP_REGS_mepc 32
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/** Index of mstatus member in sbi_trap_regs */
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#define SBI_TRAP_REGS_mstatus 33
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/** Index of mstatusH member in sbi_trap_regs */
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#define SBI_TRAP_REGS_mstatusH 34
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/** Last member index in sbi_trap_regs */
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#define SBI_TRAP_REGS_last 34
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#define SBI_TRAP_REGS_last 35
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/* clang-format on */
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@ -164,6 +166,8 @@ struct sbi_trap_regs {
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unsigned long mepc;
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/** mstatus register state */
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unsigned long mstatus;
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/** mstatusH register state (only for 32-bit) */
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unsigned long mstatusH;
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} __packed;
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struct sbi_scratch;
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@ -79,41 +79,119 @@ static void __noreturn sbi_trap_error(const char *msg, int rc, u32 hartid,
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int sbi_trap_redirect(struct sbi_trap_regs *regs, struct sbi_scratch *scratch,
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ulong epc, ulong cause, ulong tval)
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{
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ulong new_mstatus, prev_mode;
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ulong hstatus, vsstatus, prev_mode;
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#if __riscv_xlen == 32
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bool prev_virt = (regs->mstatusH & MSTATUSH_MPV) ? TRUE : FALSE;
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bool prev_stage2 = (regs->mstatusH & MSTATUSH_MTL) ? TRUE : FALSE;
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#else
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bool prev_virt = (regs->mstatus & MSTATUS_MPV) ? TRUE : FALSE;
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bool prev_stage2 = (regs->mstatus & MSTATUS_MTL) ? TRUE : FALSE;
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#endif
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/* By default, we redirect to HS-mode */
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bool next_virt = FALSE;
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/* Sanity check on previous mode */
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prev_mode = (regs->mstatus & MSTATUS_MPP) >> MSTATUS_MPP_SHIFT;
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if (prev_mode != PRV_S && prev_mode != PRV_U)
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return SBI_ENOTSUPP;
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/* Update S-mode exception info */
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csr_write(CSR_STVAL, tval);
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csr_write(CSR_SEPC, epc);
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csr_write(CSR_SCAUSE, cause);
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/* For certain exceptions from VS/VU-mode we redirect to VS-mode */
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if (misa_extension('H') && prev_virt && !prev_stage2) {
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switch (cause) {
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case CAUSE_FETCH_PAGE_FAULT:
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case CAUSE_LOAD_PAGE_FAULT:
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case CAUSE_STORE_PAGE_FAULT:
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next_virt = TRUE;
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break;
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default:
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break;
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};
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}
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/* Set MEPC to S-mode exception vector base */
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regs->mepc = csr_read(CSR_STVEC);
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/* Update MSTATUS MPV and MTL bits */
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#if __riscv_xlen == 32
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regs->mstatusH &= ~MSTATUSH_MPV;
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regs->mstatusH |= (next_virt) ? MSTATUSH_MPV : 0UL;
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regs->mstatusH &= ~MSTATUSH_MTL;
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#else
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regs->mstatus &= ~MSTATUS_MPV;
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regs->mstatus |= (next_virt) ? MSTATUS_MPV : 0UL;
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regs->mstatus &= ~MSTATUS_MTL;
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#endif
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/* Initial value of new MSTATUS */
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new_mstatus = regs->mstatus;
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/* Update HSTATUS for VS/VU-mode to HS-mode transition */
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if (misa_extension('H') && prev_virt && !next_virt) {
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/* Update HSTATUS SP2P, SP2V, SPV, and STL bits */
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hstatus = csr_read(CSR_HSTATUS);
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hstatus &= ~HSTATUS_SP2P;
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hstatus |= (regs->mstatus & MSTATUS_SPP) ? HSTATUS_SP2P : 0;
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hstatus &= ~HSTATUS_SP2V;
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hstatus |= (hstatus & HSTATUS_SPV) ? HSTATUS_SP2V : 0;
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hstatus &= ~HSTATUS_SPV;
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hstatus |= (prev_virt) ? HSTATUS_SPV : 0;
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hstatus &= ~HSTATUS_STL;
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hstatus |= (prev_stage2) ? HSTATUS_STL : 0;
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csr_write(CSR_HSTATUS, hstatus);
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}
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/* Clear MPP, SPP, SPIE, and SIE */
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new_mstatus &=
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~(MSTATUS_MPP | MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE);
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/* Update exception related CSRs */
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if (next_virt) {
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/* Update VS-mode exception info */
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csr_write(CSR_VSTVAL, tval);
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csr_write(CSR_VSEPC, epc);
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csr_write(CSR_VSCAUSE, cause);
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/* Set SPP */
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if (prev_mode == PRV_S)
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new_mstatus |= (1UL << MSTATUS_SPP_SHIFT);
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/* Set MEPC to VS-mode exception vector base */
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regs->mepc = csr_read(CSR_VSTVEC);
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/* Set SPIE */
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if (regs->mstatus & MSTATUS_SIE)
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new_mstatus |= (1UL << MSTATUS_SPIE_SHIFT);
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/* Set MPP to VS-mode */
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regs->mstatus &= ~MSTATUS_MPP;
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regs->mstatus |= (PRV_S << MSTATUS_MPP_SHIFT);
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/* Set MPP */
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new_mstatus |= (PRV_S << MSTATUS_MPP_SHIFT);
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/* Get VS-mode SSTATUS CSR */
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vsstatus = csr_read(CSR_VSSTATUS);
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/* Set new value in MSTATUS */
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regs->mstatus = new_mstatus;
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/* Set SPP for VS-mode */
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vsstatus &= ~SSTATUS_SPP;
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if (prev_mode == PRV_S)
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vsstatus |= (1UL << SSTATUS_SPP_SHIFT);
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/* Set SPIE for VS-mode */
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vsstatus &= ~SSTATUS_SPIE;
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if (vsstatus & SSTATUS_SIE)
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vsstatus |= (1UL << SSTATUS_SPIE_SHIFT);
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/* Clear SIE for VS-mode */
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vsstatus &= ~SSTATUS_SIE;
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/* Update VS-mode SSTATUS CSR */
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csr_write(CSR_VSSTATUS, vsstatus);
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} else {
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/* Update S-mode exception info */
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csr_write(CSR_STVAL, tval);
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csr_write(CSR_SEPC, epc);
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csr_write(CSR_SCAUSE, cause);
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/* Set MEPC to S-mode exception vector base */
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regs->mepc = csr_read(CSR_STVEC);
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/* Set MPP to S-mode */
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regs->mstatus &= ~MSTATUS_MPP;
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regs->mstatus |= (PRV_S << MSTATUS_MPP_SHIFT);
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/* Set SPP for S-mode*/
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regs->mstatus &= ~MSTATUS_SPP;
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if (prev_mode == PRV_S)
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regs->mstatus |= (1UL << MSTATUS_SPP_SHIFT);
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/* Set SPIE for S-mode */
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regs->mstatus &= ~MSTATUS_SPIE;
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if (regs->mstatus & MSTATUS_SIE)
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regs->mstatus |= (1UL << MSTATUS_SPIE_SHIFT);
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/* Clear SIE for S-mode */
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regs->mstatus &= ~MSTATUS_SIE;
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}
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return 0;
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}
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@ -195,7 +273,8 @@ void sbi_trap_handler(struct sbi_trap_regs *regs, struct sbi_scratch *scratch)
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break;
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default:
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/* If the trap came from S or U mode, redirect it there */
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rc = sbi_trap_redirect(regs, scratch, regs->mepc, mcause, mtval);
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rc = sbi_trap_redirect(regs, scratch, regs->mepc,
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mcause, mtval);
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break;
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};
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