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lib: sbi: Factor-out Smepmp configuration as separate function
Let us factor-out Smepmp configuaration as separate function so that code is more readable. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
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b8fb96eceb
commit
bff27c1fb4
1 changed files with 110 additions and 70 deletions
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@ -288,9 +288,9 @@ unsigned int sbi_hart_mhpm_bits(struct sbi_scratch *scratch)
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/*
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* Returns Smepmp flags for a given domain and region based on permissions.
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*/
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unsigned int sbi_hart_get_smepmp_flags(struct sbi_scratch *scratch,
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struct sbi_domain *dom,
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struct sbi_domain_memregion *reg)
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static unsigned int sbi_hart_get_smepmp_flags(struct sbi_scratch *scratch,
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struct sbi_domain *dom,
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struct sbi_domain_memregion *reg)
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{
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unsigned int pmp_flags = 0;
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@ -348,6 +348,103 @@ unsigned int sbi_hart_get_smepmp_flags(struct sbi_scratch *scratch,
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return pmp_flags;
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}
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static int sbi_hart_smepmp_configure(struct sbi_scratch *scratch,
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unsigned int pmp_count,
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unsigned int pmp_gran_log2,
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unsigned long pmp_addr_max)
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{
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struct sbi_domain_memregion *reg;
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struct sbi_domain *dom = sbi_domain_thishart_ptr();
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unsigned int pmp_idx = 0;
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unsigned int pmp_flags;
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unsigned long pmp_addr;
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/*
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* Set the RLB and clear MML so that, we can write to
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* entries without enforcement even if some entries
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* are locked.
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*/
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csr_set(CSR_MSECCFG, MSECCFG_RLB);
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csr_clear(CSR_MSECCFG, MSECCFG_MML);
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/* Disable the reserved entry */
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pmp_disable(SBI_SMEPMP_RESV_ENTRY);
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sbi_domain_for_each_memregion(dom, reg) {
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if (pmp_idx == SBI_SMEPMP_RESV_ENTRY)
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pmp_idx++;
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if (pmp_count <= pmp_idx)
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break;
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pmp_flags = sbi_hart_get_smepmp_flags(scratch, dom, reg);
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if (pmp_flags == 0)
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return 0;
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pmp_addr = reg->base >> PMP_SHIFT;
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if (pmp_gran_log2 <= reg->order && pmp_addr < pmp_addr_max) {
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pmp_set(pmp_idx++, pmp_flags, reg->base, reg->order);
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} else {
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sbi_printf("Can not configure pmp for domain %s because"
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" memory region address 0x%lx or size 0x%lx "
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"is not in range.\n", dom->name, reg->base,
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reg->order);
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}
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}
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/*
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* All entries are programmed. Enable MML bit.
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* Keep the RLB bit so that dynamic mappings can be done.
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*/
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csr_set(CSR_MSECCFG, (MSECCFG_RLB | MSECCFG_MML));
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return 0;
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}
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static int sbi_hart_oldpmp_configure(struct sbi_scratch *scratch,
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unsigned int pmp_count,
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unsigned int pmp_gran_log2,
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unsigned long pmp_addr_max)
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{
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struct sbi_domain_memregion *reg;
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struct sbi_domain *dom = sbi_domain_thishart_ptr();
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unsigned int pmp_idx = 0;
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unsigned int pmp_flags;
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unsigned long pmp_addr;
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sbi_domain_for_each_memregion(dom, reg) {
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if (pmp_count <= pmp_idx)
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break;
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pmp_flags = 0;
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/*
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* If permissions are to be enforced for all modes on
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* this region, the lock bit should be set.
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*/
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if (reg->flags & SBI_DOMAIN_MEMREGION_ENF_PERMISSIONS)
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pmp_flags |= PMP_L;
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if (reg->flags & SBI_DOMAIN_MEMREGION_SU_READABLE)
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pmp_flags |= PMP_R;
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if (reg->flags & SBI_DOMAIN_MEMREGION_SU_WRITABLE)
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pmp_flags |= PMP_W;
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if (reg->flags & SBI_DOMAIN_MEMREGION_SU_EXECUTABLE)
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pmp_flags |= PMP_X;
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pmp_addr = reg->base >> PMP_SHIFT;
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if (pmp_gran_log2 <= reg->order && pmp_addr < pmp_addr_max) {
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pmp_set(pmp_idx++, pmp_flags, reg->base, reg->order);
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} else {
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sbi_printf("Can not configure pmp for domain %s because"
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" memory region address 0x%lx or size 0x%lx "
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"is not in range.\n", dom->name, reg->base,
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reg->order);
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}
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}
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return 0;
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}
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int sbi_hart_map_saddr(unsigned long addr, unsigned long size)
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{
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/* shared R/W access for M and S/U mode */
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@ -392,12 +489,10 @@ int sbi_hart_unmap_saddr(void)
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int sbi_hart_pmp_configure(struct sbi_scratch *scratch)
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{
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struct sbi_domain_memregion *reg;
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struct sbi_domain *dom = sbi_domain_thishart_ptr();
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unsigned int pmp_idx = 0;
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unsigned int pmp_flags, pmp_bits, pmp_gran_log2;
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int rc;
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unsigned int pmp_bits, pmp_gran_log2;
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unsigned int pmp_count = sbi_hart_pmp_count(scratch);
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unsigned long pmp_addr = 0, pmp_addr_max = 0;
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unsigned long pmp_addr_max;
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if (!pmp_count)
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return 0;
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@ -406,67 +501,12 @@ int sbi_hart_pmp_configure(struct sbi_scratch *scratch)
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pmp_bits = sbi_hart_pmp_addrbits(scratch) - 1;
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pmp_addr_max = (1UL << pmp_bits) | ((1UL << pmp_bits) - 1);
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if (sbi_hart_has_extension(scratch, SBI_HART_EXT_SMEPMP)) {
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/* Reserve first entry for dynamic shared mappings */
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pmp_idx = SBI_SMEPMP_RESV_ENTRY + 1;
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/*
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* Set the RLB and clear MML so that, we can write to
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* entries without enforcement even if some entries
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* are locked.
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*/
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csr_set(CSR_MSECCFG, MSECCFG_RLB);
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csr_clear(CSR_MSECCFG, MSECCFG_MML);
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/* Disable the reserved entry */
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pmp_disable(SBI_SMEPMP_RESV_ENTRY);
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}
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sbi_domain_for_each_memregion(dom, reg) {
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if (pmp_count <= pmp_idx)
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break;
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pmp_flags = 0;
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if (sbi_hart_has_extension(scratch, SBI_HART_EXT_SMEPMP)) {
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pmp_flags = sbi_hart_get_smepmp_flags(scratch, dom, reg);
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if (pmp_flags == 0)
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return 0;
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} else {
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/*
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* If permissions are to be enforced for all modes on
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* this region, the lock bit should be set.
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*/
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if (reg->flags & SBI_DOMAIN_MEMREGION_ENF_PERMISSIONS)
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pmp_flags |= PMP_L;
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if (reg->flags & SBI_DOMAIN_MEMREGION_SU_READABLE)
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pmp_flags |= PMP_R;
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if (reg->flags & SBI_DOMAIN_MEMREGION_SU_WRITABLE)
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pmp_flags |= PMP_W;
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if (reg->flags & SBI_DOMAIN_MEMREGION_SU_EXECUTABLE)
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pmp_flags |= PMP_X;
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}
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pmp_addr = reg->base >> PMP_SHIFT;
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if (pmp_gran_log2 <= reg->order && pmp_addr < pmp_addr_max) {
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pmp_set(pmp_idx++, pmp_flags, reg->base, reg->order);
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} else {
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sbi_printf("Can not configure pmp for domain %s because"
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" memory region address 0x%lx or size 0x%lx "
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"is not in range.\n", dom->name, reg->base,
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reg->order);
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}
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}
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if (sbi_hart_has_extension(scratch, SBI_HART_EXT_SMEPMP)) {
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/*
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* All entries are programmed. Enable MML bit.
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* Keep the RLB bit so that dynamic mappings can be done.
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*/
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csr_set(CSR_MSECCFG, (MSECCFG_RLB | MSECCFG_MML));
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}
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if (sbi_hart_has_extension(scratch, SBI_HART_EXT_SMEPMP))
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rc = sbi_hart_smepmp_configure(scratch, pmp_count,
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pmp_gran_log2, pmp_addr_max);
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else
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rc = sbi_hart_oldpmp_configure(scratch, pmp_count,
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pmp_gran_log2, pmp_addr_max);
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/*
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* As per section 3.7.2 of privileged specification v1.12,
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@ -489,7 +529,7 @@ int sbi_hart_pmp_configure(struct sbi_scratch *scratch)
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__sbi_hfence_gvma_all();
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}
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return 0;
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return rc;
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}
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int sbi_hart_priv_version(struct sbi_scratch *scratch)
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