mirror of
https://github.com/Fishwaldo/opensbi.git
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utils/reset: Remove fdt_reset_thead
In the past, we used fdt_reset_thead to help customers with prototype verification. However, with the emergence of the Big-little SoC system, it can no longer meet the demand. Therefore, we use zero_stage_boot instead of fdt_reset_thead. It cleans up the opensbi code and ends the disputation of reset_sample's dts. This patch removes the fdt_reset_thead component and updates the related doc. Signed-off-by: Guo Ren <guoren@linux.alibaba.com> Signed-off-by: Guo Ren <guoren@kernel.org> Reviewed-by: Anup Patel <anup@brainfault.org>
This commit is contained in:
Guo Ren
Anup Patel
parent
fccdf41d32
commit
d1e0f7f25b
7 changed files with 7 additions and 389 deletions
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@ -1,7 +1,7 @@
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T-HEAD C9xx Series Processors
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=============================
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The **C9xx** series processors are high-performance RISC-V architecture
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The C9xx series processors are high-performance RISC-V architecture
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multi-core processors with AI vector acceleration engine.
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For more details, refer [T-HEAD.CN](https://www.t-head.cn/)
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@ -12,185 +12,16 @@ To build the platform-specific library and firmware images, provide the
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Platform Options
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----------------
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The *T-HEAD C9xx* does not have any platform-specific compile options
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The T-HEAD C9xx does not have any platform-specific compile options
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because it uses generic platform.
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```
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CROSS_COMPILE=riscv64-linux-gnu- PLATFORM=generic /usr/bin/make
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CROSS_COMPILE=riscv64-linux-gnu- PLATFORM=generic make
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```
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The *T-HEAD C9xx* DTB provided to OpenSBI generic firmwares will usually have
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"riscv,clint0", "riscv,plic0", "thead,reset-sample" compatible strings.
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Here is the simplest boot flow for a fpga prototype:
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DTS Example1: (Single core, eg: Allwinner D1 - c906)
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----------------------------------------------------
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(Jtag gdbinit) -> (zsb) -> (opensbi) -> (linux)
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```
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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timebase-frequency = <3000000>;
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cpu@0 {
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device_type = "cpu";
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reg = <0>;
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status = "okay";
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compatible = "riscv";
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riscv,isa = "rv64imafdcv";
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mmu-type = "riscv,sv39";
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cpu0_intc: interrupt-controller {
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#interrupt-cells = <1>;
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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};
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};
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};
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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compatible = "simple-bus";
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ranges;
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clint0: clint@14000000 {
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compatible = "allwinner,sun20i-d1-clint";
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interrupts-extended = <
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&cpu0_intc 3 &cpu0_intc 7
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>;
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reg = <0x0 0x14000000 0x0 0x04000000>;
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};
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intc: interrupt-controller@10000000 {
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#interrupt-cells = <1>;
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compatible = "allwinner,sun20i-d1-plic",
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"thead,c900-plic";
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interrupt-controller;
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interrupts-extended = <
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&cpu0_intc 0xffffffff &cpu0_intc 9
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>;
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reg = <0x0 0x10000000 0x0 0x04000000>;
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reg-names = "control";
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riscv,max-priority = <7>;
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riscv,ndev = <200>;
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};
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}
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```
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DTS Example2: (Multi cores with soc reset-regs)
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-----------------------------------------------
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```
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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timebase-frequency = <3000000>;
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cpu@0 {
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device_type = "cpu";
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reg = <0>;
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status = "okay";
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compatible = "riscv";
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riscv,isa = "rv64imafdc";
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mmu-type = "riscv,sv39";
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cpu0_intc: interrupt-controller {
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#interrupt-cells = <1>;
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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};
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};
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cpu@1 {
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device_type = "cpu";
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reg = <1>;
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status = "fail";
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compatible = "riscv";
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riscv,isa = "rv64imafdc";
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mmu-type = "riscv,sv39";
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cpu1_intc: interrupt-controller {
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#interrupt-cells = <1>;
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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};
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};
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cpu@2 {
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device_type = "cpu";
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reg = <2>;
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status = "fail";
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compatible = "riscv";
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riscv,isa = "rv64imafdc";
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mmu-type = "riscv,sv39";
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cpu2_intc: interrupt-controller {
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#interrupt-cells = <1>;
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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};
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};
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cpu@3 {
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device_type = "cpu";
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reg = <3>;
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status = "fail";
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compatible = "riscv";
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riscv,isa = "rv64imafdc";
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mmu-type = "riscv,sv39";
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cpu3_intc: interrupt-controller {
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#interrupt-cells = <1>;
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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};
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};
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};
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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compatible = "simple-bus";
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ranges;
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reset: reset-sample {
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compatible = "thead,reset-sample";
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entry-reg = <0xff 0xff019050>;
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entry-cnt = <4>;
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control-reg = <0xff 0xff015004>;
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control-val = <0x1c>;
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csr-copy = <0x7f3 0x7c0 0x7c1 0x7c2 0x7c3 0x7c5 0x7cc>;
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};
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clint0: clint@ffdc000000 {
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compatible = "riscv,clint0";
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interrupts-extended = <
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&cpu0_intc 3 &cpu0_intc 7
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&cpu1_intc 3 &cpu1_intc 7
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&cpu2_intc 3 &cpu2_intc 7
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&cpu3_intc 3 &cpu3_intc 7
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&cpu4_intc 3 &cpu4_intc 7
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>;
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reg = <0xff 0xdc000000 0x0 0x04000000>;
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};
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intc: interrupt-controller@ffd8000000 {
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#interrupt-cells = <1>;
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compatible = "thead,c900-plic";
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interrupt-controller;
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interrupts-extended = <
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&cpu0_intc 0xffffffff &cpu0_intc 9
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&cpu1_intc 0xffffffff &cpu1_intc 9
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&cpu2_intc 0xffffffff &cpu2_intc 9
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&cpu3_intc 0xffffffff &cpu3_intc 9
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>;
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reg = <0xff 0xd8000000 0x0 0x04000000>;
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reg-names = "control";
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riscv,max-priority = <7>;
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riscv,ndev = <80>;
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};
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}
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```
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DTS Example2: (Multi cores with old reset csrs)
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-----------------------------------------------
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```
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reset: reset-sample {
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compatible = "thead,reset-sample";
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using-csr-reset;
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csr-copy = <0x7c0 0x7c1 0x7c2 0x7c3 0x7c5 0x7cc
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0x3b0 0x3b1 0x3b2 0x3b3
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0x3b4 0x3b5 0x3b6 0x3b7
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0x3a0>;
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};
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```
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For more details, refer:
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[zero stage boot](https://github.com/c-sky/zero_stage_boot)
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@ -33,10 +33,6 @@ config FDT_RESET_SYSCON
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depends on FDT_REGMAP
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default n
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config FDT_RESET_THEAD
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bool "T-HEAD FDT reset driver"
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default n
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endif
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endmenu
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@ -1,134 +0,0 @@
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/*
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* SPDX-License-Identifier: BSD-2-Clause
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*/
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#include <libfdt.h>
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#include <sbi/riscv_io.h>
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#include <sbi/sbi_bitops.h>
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#include <sbi/sbi_hart.h>
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#include <sbi/sbi_scratch.h>
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#include <sbi/sbi_system.h>
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#include <sbi_utils/fdt/fdt_helper.h>
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#include <sbi_utils/reset/fdt_reset.h>
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#include "fdt_reset_thead.h"
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struct custom_csr custom_csr[MAX_CUSTOM_CSR];
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#define CSR_OPCODE 0x39073
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static void clone_csrs(int cnt)
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{
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unsigned long i;
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for (i = 0; i < cnt; i++) {
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/* Write csr BIT[31 - 20] to stub */
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__reset_thead_csr_stub[3*i + 1] =
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CSR_OPCODE | (custom_csr[i].index << 20);
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/* Mask csr BIT[31 - 20] */
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*(u32 *)&__fdt_reset_thead_csrr &= BIT(20) - 1;
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smp_mb();
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/* Write csr BIT[31 - 20] to __fdt_reset_thead_csrr */
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*(u32 *)&__fdt_reset_thead_csrr |= custom_csr[i].index << 20;
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smp_mb();
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RISCV_FENCE_I;
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custom_csr[i].value = __fdt_reset_thead_csrr();
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}
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}
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static int thead_system_reset_check(u32 type, u32 reason)
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{
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return 1;
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}
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static void thead_system_reset(u32 type, u32 reason)
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{
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ebreak();
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}
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static struct sbi_system_reset_device thead_reset = {
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.name = "thead_reset",
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.system_reset_check = thead_system_reset_check,
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.system_reset = thead_system_reset
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};
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extern void __thead_pre_start_warm(void);
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static int thead_reset_init(void *fdt, int nodeoff,
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const struct fdt_match *match)
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{
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char *p;
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const fdt64_t *val;
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const fdt32_t *val_w;
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int len, i;
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u32 t, tmp = 0;
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/* Prepare clone csrs */
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val_w = fdt_getprop(fdt, nodeoff, "csr-copy", &len);
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if (len > 0 && val_w) {
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int cnt;
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cnt = len / sizeof(fdt32_t);
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if (cnt > MAX_CUSTOM_CSR)
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sbi_hart_hang();
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for (i = 0; i < cnt; i++) {
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custom_csr[i].index = fdt32_to_cpu(val_w[i]);
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}
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if (cnt)
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clone_csrs(cnt);
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}
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/* Old reset method for secondary harts */
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if (fdt_getprop(fdt, nodeoff, "using-csr-reset", &len)) {
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csr_write(0x7c7, (ulong)&__thead_pre_start_warm);
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csr_write(0x7c6, -1);
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}
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/* Custom reset method for secondary harts */
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val = fdt_getprop(fdt, nodeoff, "entry-reg", &len);
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if (len > 0 && val) {
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p = (char *)(ulong)fdt64_to_cpu(*val);
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val_w = fdt_getprop(fdt, nodeoff, "entry-cnt", &len);
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if (len > 0 && val_w) {
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tmp = fdt32_to_cpu(*val_w);
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for (i = 0; i < tmp; i++) {
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t = (ulong)&__thead_pre_start_warm;
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writel(t, p + (8 * i));
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t = (u64)(ulong)&__thead_pre_start_warm >> 32;
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writel(t, p + (8 * i) + 4);
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}
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}
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val = fdt_getprop(fdt, nodeoff, "control-reg", &len);
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if (len > 0 && val) {
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p = (void *)(ulong)fdt64_to_cpu(*val);
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val_w = fdt_getprop(fdt, nodeoff, "control-val", &len);
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if (len > 0 && val_w) {
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tmp = fdt32_to_cpu(*val_w);
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tmp |= readl(p);
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writel(tmp, p);
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}
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}
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}
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sbi_system_reset_add_device(&thead_reset);
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return 0;
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}
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static const struct fdt_match thead_reset_match[] = {
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{ .compatible = "thead,reset-sample" },
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{ },
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};
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struct fdt_reset fdt_reset_thead = {
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.match_table = thead_reset_match,
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.init = thead_reset_init
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};
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@ -1,23 +0,0 @@
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/*
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* SPDX-License-Identifier: BSD-2-Clause
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*/
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#ifndef __FDT_RESET_THEAD_H__
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#define __FDT_RESET_THEAD_H__
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#define MAX_CUSTOM_CSR 32
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#ifndef __ASSEMBLER__
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struct custom_csr {
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unsigned long index;
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unsigned long value;
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};
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u64 __fdt_reset_thead_csrr(void);
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extern struct custom_csr custom_csr[MAX_CUSTOM_CSR];
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extern u32 __reset_thead_csr_stub[];
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#endif /* __ASSEMBLER__ */
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#endif /* __FDT_RESET_THEAD_H__ */
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@ -1,47 +0,0 @@
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/*
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* SPDX-License-Identifier: BSD-2-Clause
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*/
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#include <sbi/riscv_asm.h>
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#include "fdt_reset_thead.h"
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/*
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* csrrs rd, csr, rs1
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* |31 20|19 15|14 12|11 7|6 0|
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* csr rs1 010 rd 1110011
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*/
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#define CSR_STUB addi x0, x0, 0
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.option norvc
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.align 3
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.global __fdt_reset_thead_csrr
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__fdt_reset_thead_csrr:
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csrrs a0, 0, x0
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ret
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.align 3
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.global __thead_pre_start_warm
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__thead_pre_start_warm:
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/*
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* Clear L1 cache & BTB & BHT ...
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*/
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li t1, 0x70013
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csrw 0x7c2, t1
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fence rw,rw
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lla t1, custom_csr
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.global __reset_thead_csr_stub
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__reset_thead_csr_stub:
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.rept MAX_CUSTOM_CSR
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REG_L t2, 8(t1)
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CSR_STUB
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addi t1, t1, 16
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.endr
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/*
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* Clear L1 cache & BTB & BHT ...
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*/
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li t1, 0x70013
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csrw 0x7c2, t1
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fence rw,rw
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j _start_warm
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@ -26,7 +26,3 @@ libsbiutils-objs-$(CONFIG_FDT_RESET_SUNXI_WDT) += reset/fdt_reset_sunxi_wdt.o
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carray-fdt_reset_drivers-$(CONFIG_FDT_RESET_SYSCON) += fdt_syscon_poweroff
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carray-fdt_reset_drivers-$(CONFIG_FDT_RESET_SYSCON) += fdt_syscon_reboot
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libsbiutils-objs-$(CONFIG_FDT_RESET_SYSCON) += reset/fdt_reset_syscon.o
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carray-fdt_reset_drivers-$(CONFIG_FDT_RESET_THEAD) += fdt_reset_thead
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libsbiutils-objs-$(CONFIG_FDT_RESET_THEAD) += reset/fdt_reset_thead.o
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libsbiutils-objs-$(CONFIG_FDT_RESET_THEAD) += reset/fdt_reset_thead_asm.o
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@ -27,7 +27,6 @@ CONFIG_FDT_RESET_GPIO=y
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CONFIG_FDT_RESET_HTIF=y
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CONFIG_FDT_RESET_SUNXI_WDT=y
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CONFIG_FDT_RESET_SYSCON=y
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CONFIG_FDT_RESET_THEAD=y
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CONFIG_FDT_SERIAL=y
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CONFIG_FDT_SERIAL_CADENCE=y
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CONFIG_FDT_SERIAL_GAISLER=y
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