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include: Move RISCV_TRAP_REGS_xyz defines to sbi_trap.h
The struct sbi_trap_regs related defines RISCV_TRAP_REGS_xyz should be in sbi_trap.h so that we can keep these defines in-sync with changes in struct sbi_trap_regs. Signed-off-by: Anup Patel <anup.patel@wdc.com>
This commit is contained in:
Anup Patel
Anup Patel
parent
5ed3cf3707
commit
dc7be34d52
3 changed files with 114 additions and 109 deletions
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@ -11,6 +11,7 @@
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#include <sbi/riscv_encoding.h>
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#include <sbi/sbi_platform.h>
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#include <sbi/sbi_scratch.h>
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#include <sbi/sbi_trap.h>
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.align 3
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.section .entry, "ax", %progbits
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@ -236,18 +237,18 @@ _trap_handler:
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csrrw sp, mscratch, sp
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/* Setup exception stack */
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add sp, sp, -(RISCV_TRAP_REGS_SIZE)
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add sp, sp, -(SBI_TRAP_REGS_SIZE)
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/* Save RA, T0, T1, and T2 */
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REG_S ra, RISCV_TRAP_REGS_OFFSET(ra)(sp)
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REG_S t0, RISCV_TRAP_REGS_OFFSET(t0)(sp)
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REG_S t1, RISCV_TRAP_REGS_OFFSET(t1)(sp)
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REG_S t2, RISCV_TRAP_REGS_OFFSET(t2)(sp)
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REG_S ra, SBI_TRAP_REGS_OFFSET(ra)(sp)
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REG_S t0, SBI_TRAP_REGS_OFFSET(t0)(sp)
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REG_S t1, SBI_TRAP_REGS_OFFSET(t1)(sp)
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REG_S t2, SBI_TRAP_REGS_OFFSET(t2)(sp)
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/* Save original SP and restore MSCRATCH */
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add t0, sp, RISCV_TRAP_REGS_SIZE
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add t0, sp, SBI_TRAP_REGS_SIZE
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csrrw t0, mscratch, t0
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REG_S t0, RISCV_TRAP_REGS_OFFSET(sp)(sp)
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REG_S t0, SBI_TRAP_REGS_OFFSET(sp)(sp)
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/* Save MEPC and MSTATUS CSRs */
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csrr t0, mepc
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@ -261,37 +262,37 @@ _trap_handler:
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*/
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/* Save MEPC and MSTATUS CSRs */
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REG_S t0, RISCV_TRAP_REGS_OFFSET(mepc)(sp)
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REG_S t1, RISCV_TRAP_REGS_OFFSET(mstatus)(sp)
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REG_S t0, SBI_TRAP_REGS_OFFSET(mepc)(sp)
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REG_S t1, SBI_TRAP_REGS_OFFSET(mstatus)(sp)
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/* Save all general regisers except SP, RA, T0, T1, and T2 */
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REG_S zero, RISCV_TRAP_REGS_OFFSET(zero)(sp)
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REG_S gp, RISCV_TRAP_REGS_OFFSET(gp)(sp)
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REG_S tp, RISCV_TRAP_REGS_OFFSET(tp)(sp)
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REG_S s0, RISCV_TRAP_REGS_OFFSET(s0)(sp)
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REG_S s1, RISCV_TRAP_REGS_OFFSET(s1)(sp)
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REG_S a0, RISCV_TRAP_REGS_OFFSET(a0)(sp)
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REG_S a1, RISCV_TRAP_REGS_OFFSET(a1)(sp)
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REG_S a2, RISCV_TRAP_REGS_OFFSET(a2)(sp)
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REG_S a3, RISCV_TRAP_REGS_OFFSET(a3)(sp)
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REG_S a4, RISCV_TRAP_REGS_OFFSET(a4)(sp)
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REG_S a5, RISCV_TRAP_REGS_OFFSET(a5)(sp)
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REG_S a6, RISCV_TRAP_REGS_OFFSET(a6)(sp)
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REG_S a7, RISCV_TRAP_REGS_OFFSET(a7)(sp)
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REG_S s2, RISCV_TRAP_REGS_OFFSET(s2)(sp)
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REG_S s3, RISCV_TRAP_REGS_OFFSET(s3)(sp)
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REG_S s4, RISCV_TRAP_REGS_OFFSET(s4)(sp)
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REG_S s5, RISCV_TRAP_REGS_OFFSET(s5)(sp)
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REG_S s6, RISCV_TRAP_REGS_OFFSET(s6)(sp)
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REG_S s7, RISCV_TRAP_REGS_OFFSET(s7)(sp)
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REG_S s8, RISCV_TRAP_REGS_OFFSET(s8)(sp)
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REG_S s9, RISCV_TRAP_REGS_OFFSET(s9)(sp)
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REG_S s10, RISCV_TRAP_REGS_OFFSET(s10)(sp)
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REG_S s11, RISCV_TRAP_REGS_OFFSET(s11)(sp)
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REG_S t3, RISCV_TRAP_REGS_OFFSET(t3)(sp)
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REG_S t4, RISCV_TRAP_REGS_OFFSET(t4)(sp)
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REG_S t5, RISCV_TRAP_REGS_OFFSET(t5)(sp)
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REG_S t6, RISCV_TRAP_REGS_OFFSET(t6)(sp)
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REG_S zero, SBI_TRAP_REGS_OFFSET(zero)(sp)
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REG_S gp, SBI_TRAP_REGS_OFFSET(gp)(sp)
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REG_S tp, SBI_TRAP_REGS_OFFSET(tp)(sp)
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REG_S s0, SBI_TRAP_REGS_OFFSET(s0)(sp)
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REG_S s1, SBI_TRAP_REGS_OFFSET(s1)(sp)
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REG_S a0, SBI_TRAP_REGS_OFFSET(a0)(sp)
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REG_S a1, SBI_TRAP_REGS_OFFSET(a1)(sp)
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REG_S a2, SBI_TRAP_REGS_OFFSET(a2)(sp)
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REG_S a3, SBI_TRAP_REGS_OFFSET(a3)(sp)
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REG_S a4, SBI_TRAP_REGS_OFFSET(a4)(sp)
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REG_S a5, SBI_TRAP_REGS_OFFSET(a5)(sp)
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REG_S a6, SBI_TRAP_REGS_OFFSET(a6)(sp)
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REG_S a7, SBI_TRAP_REGS_OFFSET(a7)(sp)
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REG_S s2, SBI_TRAP_REGS_OFFSET(s2)(sp)
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REG_S s3, SBI_TRAP_REGS_OFFSET(s3)(sp)
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REG_S s4, SBI_TRAP_REGS_OFFSET(s4)(sp)
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REG_S s5, SBI_TRAP_REGS_OFFSET(s5)(sp)
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REG_S s6, SBI_TRAP_REGS_OFFSET(s6)(sp)
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REG_S s7, SBI_TRAP_REGS_OFFSET(s7)(sp)
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REG_S s8, SBI_TRAP_REGS_OFFSET(s8)(sp)
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REG_S s9, SBI_TRAP_REGS_OFFSET(s9)(sp)
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REG_S s10, SBI_TRAP_REGS_OFFSET(s10)(sp)
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REG_S s11, SBI_TRAP_REGS_OFFSET(s11)(sp)
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REG_S t3, SBI_TRAP_REGS_OFFSET(t3)(sp)
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REG_S t4, SBI_TRAP_REGS_OFFSET(t4)(sp)
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REG_S t5, SBI_TRAP_REGS_OFFSET(t5)(sp)
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REG_S t6, SBI_TRAP_REGS_OFFSET(t6)(sp)
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/* Call C routine */
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add a0, sp, zero
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@ -299,36 +300,36 @@ _trap_handler:
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call sbi_trap_handler
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/* Restore all general regisers except SP, RA, T0, T1, T2, and T3 */
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REG_L gp, RISCV_TRAP_REGS_OFFSET(gp)(sp)
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REG_L tp, RISCV_TRAP_REGS_OFFSET(tp)(sp)
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REG_L s0, RISCV_TRAP_REGS_OFFSET(s0)(sp)
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REG_L s1, RISCV_TRAP_REGS_OFFSET(s1)(sp)
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REG_L a0, RISCV_TRAP_REGS_OFFSET(a0)(sp)
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REG_L a1, RISCV_TRAP_REGS_OFFSET(a1)(sp)
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REG_L a2, RISCV_TRAP_REGS_OFFSET(a2)(sp)
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REG_L a3, RISCV_TRAP_REGS_OFFSET(a3)(sp)
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REG_L a4, RISCV_TRAP_REGS_OFFSET(a4)(sp)
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REG_L a5, RISCV_TRAP_REGS_OFFSET(a5)(sp)
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REG_L a6, RISCV_TRAP_REGS_OFFSET(a6)(sp)
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REG_L a7, RISCV_TRAP_REGS_OFFSET(a7)(sp)
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REG_L s2, RISCV_TRAP_REGS_OFFSET(s2)(sp)
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REG_L s3, RISCV_TRAP_REGS_OFFSET(s3)(sp)
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REG_L s4, RISCV_TRAP_REGS_OFFSET(s4)(sp)
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REG_L s5, RISCV_TRAP_REGS_OFFSET(s5)(sp)
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REG_L s6, RISCV_TRAP_REGS_OFFSET(s6)(sp)
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REG_L s7, RISCV_TRAP_REGS_OFFSET(s7)(sp)
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REG_L s8, RISCV_TRAP_REGS_OFFSET(s8)(sp)
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REG_L s9, RISCV_TRAP_REGS_OFFSET(s9)(sp)
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REG_L s10, RISCV_TRAP_REGS_OFFSET(s10)(sp)
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REG_L s11, RISCV_TRAP_REGS_OFFSET(s11)(sp)
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REG_L t3, RISCV_TRAP_REGS_OFFSET(t3)(sp)
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REG_L t4, RISCV_TRAP_REGS_OFFSET(t4)(sp)
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REG_L t5, RISCV_TRAP_REGS_OFFSET(t5)(sp)
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REG_L t6, RISCV_TRAP_REGS_OFFSET(t6)(sp)
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REG_L gp, SBI_TRAP_REGS_OFFSET(gp)(sp)
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REG_L tp, SBI_TRAP_REGS_OFFSET(tp)(sp)
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REG_L s0, SBI_TRAP_REGS_OFFSET(s0)(sp)
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REG_L s1, SBI_TRAP_REGS_OFFSET(s1)(sp)
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REG_L a0, SBI_TRAP_REGS_OFFSET(a0)(sp)
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REG_L a1, SBI_TRAP_REGS_OFFSET(a1)(sp)
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REG_L a2, SBI_TRAP_REGS_OFFSET(a2)(sp)
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REG_L a3, SBI_TRAP_REGS_OFFSET(a3)(sp)
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REG_L a4, SBI_TRAP_REGS_OFFSET(a4)(sp)
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REG_L a5, SBI_TRAP_REGS_OFFSET(a5)(sp)
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REG_L a6, SBI_TRAP_REGS_OFFSET(a6)(sp)
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REG_L a7, SBI_TRAP_REGS_OFFSET(a7)(sp)
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REG_L s2, SBI_TRAP_REGS_OFFSET(s2)(sp)
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REG_L s3, SBI_TRAP_REGS_OFFSET(s3)(sp)
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REG_L s4, SBI_TRAP_REGS_OFFSET(s4)(sp)
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REG_L s5, SBI_TRAP_REGS_OFFSET(s5)(sp)
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REG_L s6, SBI_TRAP_REGS_OFFSET(s6)(sp)
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REG_L s7, SBI_TRAP_REGS_OFFSET(s7)(sp)
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REG_L s8, SBI_TRAP_REGS_OFFSET(s8)(sp)
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REG_L s9, SBI_TRAP_REGS_OFFSET(s9)(sp)
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REG_L s10, SBI_TRAP_REGS_OFFSET(s10)(sp)
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REG_L s11, SBI_TRAP_REGS_OFFSET(s11)(sp)
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REG_L t3, SBI_TRAP_REGS_OFFSET(t3)(sp)
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REG_L t4, SBI_TRAP_REGS_OFFSET(t4)(sp)
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REG_L t5, SBI_TRAP_REGS_OFFSET(t5)(sp)
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REG_L t6, SBI_TRAP_REGS_OFFSET(t6)(sp)
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/* Load T0 and T1 with MEPC and MSTATUS */
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REG_L t0, RISCV_TRAP_REGS_OFFSET(mepc)(sp)
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REG_L t1, RISCV_TRAP_REGS_OFFSET(mstatus)(sp)
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REG_L t0, SBI_TRAP_REGS_OFFSET(mepc)(sp)
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REG_L t1, SBI_TRAP_REGS_OFFSET(mstatus)(sp)
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/*
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* Note: Jump here after fast trap handling
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@ -342,12 +343,12 @@ _trap_handler:
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csrw mstatus, t1
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/* Restore RA, T0, T1, and T2 */
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REG_L ra, RISCV_TRAP_REGS_OFFSET(ra)(sp)
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REG_L t0, RISCV_TRAP_REGS_OFFSET(t0)(sp)
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REG_L t1, RISCV_TRAP_REGS_OFFSET(t1)(sp)
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REG_L t2, RISCV_TRAP_REGS_OFFSET(t2)(sp)
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REG_L ra, SBI_TRAP_REGS_OFFSET(ra)(sp)
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REG_L t0, SBI_TRAP_REGS_OFFSET(t0)(sp)
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REG_L t1, SBI_TRAP_REGS_OFFSET(t1)(sp)
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REG_L t2, SBI_TRAP_REGS_OFFSET(t2)(sp)
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/* Restore SP */
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REG_L sp, RISCV_TRAP_REGS_OFFSET(sp)(sp)
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REG_L sp, SBI_TRAP_REGS_OFFSET(sp)(sp)
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mret
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@ -69,46 +69,6 @@
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#error "Unexpected __SIZEOF_SHORT__"
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#endif
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#define RISCV_TRAP_REGS_zero 0
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#define RISCV_TRAP_REGS_ra 1
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#define RISCV_TRAP_REGS_sp 2
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#define RISCV_TRAP_REGS_gp 3
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#define RISCV_TRAP_REGS_tp 4
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#define RISCV_TRAP_REGS_t0 5
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#define RISCV_TRAP_REGS_t1 6
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#define RISCV_TRAP_REGS_t2 7
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#define RISCV_TRAP_REGS_s0 8
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#define RISCV_TRAP_REGS_s1 9
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#define RISCV_TRAP_REGS_a0 10
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#define RISCV_TRAP_REGS_a1 11
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#define RISCV_TRAP_REGS_a2 12
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#define RISCV_TRAP_REGS_a3 13
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#define RISCV_TRAP_REGS_a4 14
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#define RISCV_TRAP_REGS_a5 15
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#define RISCV_TRAP_REGS_a6 16
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#define RISCV_TRAP_REGS_a7 17
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#define RISCV_TRAP_REGS_s2 18
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#define RISCV_TRAP_REGS_s3 19
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#define RISCV_TRAP_REGS_s4 20
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#define RISCV_TRAP_REGS_s5 21
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#define RISCV_TRAP_REGS_s6 22
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#define RISCV_TRAP_REGS_s7 23
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#define RISCV_TRAP_REGS_s8 24
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#define RISCV_TRAP_REGS_s9 25
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#define RISCV_TRAP_REGS_s10 26
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#define RISCV_TRAP_REGS_s11 27
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#define RISCV_TRAP_REGS_t3 28
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#define RISCV_TRAP_REGS_t4 29
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#define RISCV_TRAP_REGS_t5 30
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#define RISCV_TRAP_REGS_t6 31
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#define RISCV_TRAP_REGS_mepc 32
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#define RISCV_TRAP_REGS_mstatus 33
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#define RISCV_TRAP_REGS_last 34
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#define RISCV_TRAP_REGS_OFFSET(x) \
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((RISCV_TRAP_REGS_##x) * __SIZEOF_POINTER__)
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#define RISCV_TRAP_REGS_SIZE RISCV_TRAP_REGS_OFFSET(last)
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#ifndef __ASSEMBLY__
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#define csr_swap(csr, val) \
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@ -10,6 +10,48 @@
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#ifndef __SBI_TRAP_H__
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#define __SBI_TRAP_H__
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#define SBI_TRAP_REGS_zero 0
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#define SBI_TRAP_REGS_ra 1
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#define SBI_TRAP_REGS_sp 2
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#define SBI_TRAP_REGS_gp 3
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#define SBI_TRAP_REGS_tp 4
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#define SBI_TRAP_REGS_t0 5
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#define SBI_TRAP_REGS_t1 6
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#define SBI_TRAP_REGS_t2 7
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#define SBI_TRAP_REGS_s0 8
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#define SBI_TRAP_REGS_s1 9
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#define SBI_TRAP_REGS_a0 10
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#define SBI_TRAP_REGS_a1 11
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#define SBI_TRAP_REGS_a2 12
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#define SBI_TRAP_REGS_a3 13
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#define SBI_TRAP_REGS_a4 14
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#define SBI_TRAP_REGS_a5 15
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#define SBI_TRAP_REGS_a6 16
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#define SBI_TRAP_REGS_a7 17
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#define SBI_TRAP_REGS_s2 18
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#define SBI_TRAP_REGS_s3 19
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#define SBI_TRAP_REGS_s4 20
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#define SBI_TRAP_REGS_s5 21
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#define SBI_TRAP_REGS_s6 22
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#define SBI_TRAP_REGS_s7 23
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#define SBI_TRAP_REGS_s8 24
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#define SBI_TRAP_REGS_s9 25
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#define SBI_TRAP_REGS_s10 26
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#define SBI_TRAP_REGS_s11 27
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#define SBI_TRAP_REGS_t3 28
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#define SBI_TRAP_REGS_t4 29
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#define SBI_TRAP_REGS_t5 30
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#define SBI_TRAP_REGS_t6 31
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#define SBI_TRAP_REGS_mepc 32
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#define SBI_TRAP_REGS_mstatus 33
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#define SBI_TRAP_REGS_last 34
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#define SBI_TRAP_REGS_OFFSET(x) \
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((SBI_TRAP_REGS_##x) * __SIZEOF_POINTER__)
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#define SBI_TRAP_REGS_SIZE SBI_TRAP_REGS_OFFSET(last)
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#ifndef __ASSEMBLY__
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#include <sbi/sbi_types.h>
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struct sbi_trap_regs {
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@ -59,3 +101,5 @@ void sbi_trap_handler(struct sbi_trap_regs *regs,
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struct sbi_scratch *scratch);
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#endif
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#endif
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