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Fix baud rate divisor computation for U540.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
This commit is contained in:
parent
3250fe7299
commit
e0a660ec5b
2 changed files with 46 additions and 5 deletions
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@ -8,6 +8,7 @@
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*/
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#include <sbi/riscv_io.h>
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#include <sbi/sbi_console.h>
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#include <plat/serial/sifive-uart.h>
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#define UART_REG_TXFIFO 0
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@ -28,6 +29,29 @@ static volatile void *uart_base;
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static u32 uart_in_freq;
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static u32 uart_baudrate;
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/**
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* Find minimum divisor divides in_freq to max_target_hz;
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* Based on uart driver n SiFive FSBL.
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*
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* f_baud = f_in / (div + 1) => div = (f_in / f_baud) - 1
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* The nearest integer solution requires rounding up as to not exceed max_target_hz.
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* div = ceil(f_in / f_baud) - 1
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* = floor((f_in - 1 + f_baud) / f_baud) - 1
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* This should not overflow as long as (f_in - 1 + f_baud) does not exceed
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* 2^32 - 1, which is unlikely since we represent frequencies in kHz.
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*/
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static inline unsigned int uart_min_clk_divisor(uint64_t in_freq,
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uint64_t max_target_hz)
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{
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uint64_t quotient = (in_freq + max_target_hz - 1) / (max_target_hz);
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// Avoid underflow
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if (quotient == 0) {
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return 0;
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} else {
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return quotient - 1;
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}
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}
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static u32 get_reg(u32 num)
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{
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return readl(uart_base + (num * 0x4));
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@ -61,7 +85,7 @@ int sifive_uart_init(unsigned long base,
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uart_baudrate = baudrate;
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/* Configure baudrate */
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set_reg(UART_REG_DIV, (in_freq / baudrate) - 1);
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set_reg(UART_REG_DIV, uart_min_clk_divisor(in_freq, baudrate));
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/* Disable interrupts */
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set_reg(UART_REG_IE, 0);
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/* Enable TX */
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@ -10,12 +10,12 @@
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#include <sbi/riscv_encoding.h>
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#include <sbi/sbi_const.h>
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#include <sbi/sbi_platform.h>
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#include <sbi/riscv_io.h>
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#include <plat/irqchip/plic.h>
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#include <plat/serial/sifive-uart.h>
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#include <plat/sys/clint.h>
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#define SIFIVE_U_SYS_CLK 1000000000
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#define SIFIVE_U_PERIPH_CLK (SIFIVE_U_SYS_CLK / 2)
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#define SIFIVE_U_CLINT_ADDR 0x2000000
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@ -23,8 +23,15 @@
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#define SIFIVE_U_PLIC_NUM_SOURCES 0x35
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#define SIFIVE_U_PLIC_NUM_PRIORITIES 7
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#define SIFIVE_U_UART0_ADDR 0x10013000
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#define SIFIVE_U_UART1_ADDR 0x10023000
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#define SIFIVE_U_UART0_ADDR 0x10010000
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#define SIFIVE_U_UART1_ADDR 0x10011000
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#define SIFIVE_UART_BAUDRATE 115200
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/* PRCI clock related macros */
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//TODO: Do we need a separate driver for this ?
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#define SIFIVE_PRCI_BASE_ADDR 0x10000000
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#define SIFIVE_PRCI_CLKMUXSTATUSREG 0x002C
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#define SIFIVE_PRCI_CLKMUX_STATUS_TLCLKSEL (0x1 << 1)
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static int sifive_u_cold_final_init(void)
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{
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@ -57,8 +64,18 @@ static int sifive_u_pmp_region_info(u32 target_hart, u32 index,
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static int sifive_u_console_init(void)
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{
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unsigned long peri_in_freq;
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if (readl((volatile void *)SIFIVE_PRCI_BASE_ADDR +
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SIFIVE_PRCI_CLKMUXSTATUSREG) &
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SIFIVE_PRCI_CLKMUX_STATUS_TLCLKSEL){
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peri_in_freq = SIFIVE_U_SYS_CLK;
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} else {
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peri_in_freq = SIFIVE_U_SYS_CLK / 2;
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}
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return sifive_uart_init(SIFIVE_U_UART0_ADDR,
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SIFIVE_U_PERIPH_CLK, 115200);
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peri_in_freq, SIFIVE_UART_BAUDRATE);
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}
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static int sifive_u_cold_irqchip_init(void)
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