From e0d6914b3c40c1609ccf196fa448ea6880ff23d5 Mon Sep 17 00:00:00 2001
From: Anup Patel <anup.patel@wdc.com>
Date: Mon, 31 Dec 2018 11:19:20 +0530
Subject: [PATCH] include: Move RISCV_SCRATCH_xyz defines to sbi_scratch.h

The struct sbi_scratch related defines RISCV_SCRATCH_xyz should
be in sbi_scratch.h so that we can keep these defines in-sync
with changes in struct sbi_scratch.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
---
 firmware/fw_base.S        | 25 +++++++++++++------------
 include/sbi/riscv_asm.h   | 12 ------------
 include/sbi/sbi_scratch.h | 17 +++++++++++++++++
 3 files changed, 30 insertions(+), 24 deletions(-)

diff --git a/firmware/fw_base.S b/firmware/fw_base.S
index d426f15..d872061 100644
--- a/firmware/fw_base.S
+++ b/firmware/fw_base.S
@@ -9,6 +9,7 @@
 
 #include <sbi/riscv_asm.h>
 #include <sbi/riscv_encoding.h>
+#include <sbi/sbi_scratch.h>
 
 	.align 3
 	.section .entry, "ax", %progbits
@@ -146,34 +147,34 @@ _start_warm:
 	add	tp, tp, a5
 	mul	a5, s8, s6
 	sub	tp, tp, a5
-	li	a5, RISCV_SCRATCH_SIZE
+	li	a5, SBI_SCRATCH_SIZE
 	sub	tp, tp, a5
 	csrw	mscratch, tp
 
 	/* Initialize scratch space */
-	REG_S	zero, RISCV_SCRATCH_TMP0_OFFSET(tp)
+	REG_S	zero, SBI_SCRATCH_TMP0_OFFSET(tp)
 	la	a4, _fw_start
 	la	a5, _fw_end
 	mul	t0, s7, s8
 	add	a5, a5, t0
 	sub	a5, a5, a4
-	REG_S	a4, RISCV_SCRATCH_FW_START_OFFSET(tp)
-	REG_S	a5, RISCV_SCRATCH_FW_SIZE_OFFSET(tp)
+	REG_S	a4, SBI_SCRATCH_FW_START_OFFSET(tp)
+	REG_S	a5, SBI_SCRATCH_FW_SIZE_OFFSET(tp)
 	/* Note: fw_next_arg1() uses a0, a1, and ra */
 	call	fw_next_arg1
-	REG_S	a0, RISCV_SCRATCH_NEXT_ARG1_OFFSET(tp)
+	REG_S	a0, SBI_SCRATCH_NEXT_ARG1_OFFSET(tp)
 	/* Note: fw_next_addr() uses a0, a1, and ra */
 	call	fw_next_addr
-	REG_S	a0, RISCV_SCRATCH_NEXT_ADDR_OFFSET(tp)
+	REG_S	a0, SBI_SCRATCH_NEXT_ADDR_OFFSET(tp)
 	li	a4, PRV_S
-	REG_S	a4, RISCV_SCRATCH_NEXT_MODE_OFFSET(tp)
+	REG_S	a4, SBI_SCRATCH_NEXT_MODE_OFFSET(tp)
 	la	a4, _start_warm
-	REG_S	a4, RISCV_SCRATCH_WARMBOOT_ADDR_OFFSET(tp)
+	REG_S	a4, SBI_SCRATCH_WARMBOOT_ADDR_OFFSET(tp)
 	la	a4, platform
-	REG_S	a4, RISCV_SCRATCH_PLATFORM_ADDR_OFFSET(tp)
+	REG_S	a4, SBI_SCRATCH_PLATFORM_ADDR_OFFSET(tp)
 	la	a4, _hartid_to_scratch
-	REG_S	a4, RISCV_SCRATCH_HARTID_TO_SCRATCH_OFFSET(tp)
-	REG_S	zero, RISCV_SCRATCH_IPI_TYPE_OFFSET(tp)
+	REG_S	a4, SBI_SCRATCH_HARTID_TO_SCRATCH_OFFSET(tp)
+	REG_S	zero, SBI_SCRATCH_IPI_TYPE_OFFSET(tp)
 
 	/* Setup stack */
 	add	sp, tp, zero
@@ -211,7 +212,7 @@ _hartid_to_scratch:
 	add	s1, s1, s2
 	mul	s2, s0, a0
 	sub	s1, s1, s2
-	li	s2, RISCV_SCRATCH_SIZE
+	li	s2, SBI_SCRATCH_SIZE
 	sub	a0, s1, s2
 	REG_L	s0, (sp)
 	REG_L	s1, (__SIZEOF_POINTER__)(sp)
diff --git a/include/sbi/riscv_asm.h b/include/sbi/riscv_asm.h
index edf35ec..c169d93 100644
--- a/include/sbi/riscv_asm.h
+++ b/include/sbi/riscv_asm.h
@@ -69,18 +69,6 @@
 #error "Unexpected __SIZEOF_SHORT__"
 #endif
 
-#define RISCV_SCRATCH_TMP0_OFFSET		(0 * __SIZEOF_POINTER__)
-#define RISCV_SCRATCH_FW_START_OFFSET		(1 * __SIZEOF_POINTER__)
-#define RISCV_SCRATCH_FW_SIZE_OFFSET		(2 * __SIZEOF_POINTER__)
-#define RISCV_SCRATCH_NEXT_ARG1_OFFSET		(3 * __SIZEOF_POINTER__)
-#define RISCV_SCRATCH_NEXT_ADDR_OFFSET		(4 * __SIZEOF_POINTER__)
-#define RISCV_SCRATCH_NEXT_MODE_OFFSET		(5 * __SIZEOF_POINTER__)
-#define RISCV_SCRATCH_WARMBOOT_ADDR_OFFSET	(6 * __SIZEOF_POINTER__)
-#define RISCV_SCRATCH_PLATFORM_ADDR_OFFSET	(7 * __SIZEOF_POINTER__)
-#define RISCV_SCRATCH_HARTID_TO_SCRATCH_OFFSET	(8 * __SIZEOF_POINTER__)
-#define RISCV_SCRATCH_IPI_TYPE_OFFSET		(9 * __SIZEOF_POINTER__)
-#define RISCV_SCRATCH_SIZE			256
-
 #define RISCV_PLATFORM_NAME_OFFSET		(0x0)
 #define RISCV_PLATFORM_FEATURES_OFFSET		(0x40)
 #define RISCV_PLATFORM_HART_COUNT_OFFSET	(0x48)
diff --git a/include/sbi/sbi_scratch.h b/include/sbi/sbi_scratch.h
index d5c6f35..14c72a8 100644
--- a/include/sbi/sbi_scratch.h
+++ b/include/sbi/sbi_scratch.h
@@ -11,6 +11,21 @@
 #define __SBI_SCRATCH_H__
 
 #include <sbi/riscv_asm.h>
+
+#define SBI_SCRATCH_TMP0_OFFSET			(0 * __SIZEOF_POINTER__)
+#define SBI_SCRATCH_FW_START_OFFSET		(1 * __SIZEOF_POINTER__)
+#define SBI_SCRATCH_FW_SIZE_OFFSET		(2 * __SIZEOF_POINTER__)
+#define SBI_SCRATCH_NEXT_ARG1_OFFSET		(3 * __SIZEOF_POINTER__)
+#define SBI_SCRATCH_NEXT_ADDR_OFFSET		(4 * __SIZEOF_POINTER__)
+#define SBI_SCRATCH_NEXT_MODE_OFFSET		(5 * __SIZEOF_POINTER__)
+#define SBI_SCRATCH_WARMBOOT_ADDR_OFFSET	(6 * __SIZEOF_POINTER__)
+#define SBI_SCRATCH_PLATFORM_ADDR_OFFSET	(7 * __SIZEOF_POINTER__)
+#define SBI_SCRATCH_HARTID_TO_SCRATCH_OFFSET	(8 * __SIZEOF_POINTER__)
+#define SBI_SCRATCH_IPI_TYPE_OFFSET		(9 * __SIZEOF_POINTER__)
+#define SBI_SCRATCH_SIZE			256
+
+#ifndef __ASSEMBLY__
+
 #include <sbi/sbi_types.h>
 
 struct sbi_scratch {
@@ -33,3 +48,5 @@ struct sbi_scratch {
 ((void *)(sbi_scratch_thishart_ptr()->next_arg1))
 
 #endif
+
+#endif