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lib: sbi_misaligned_ldst: Fix handling of C.SWSP and C.SDSP
Unlike C.LWSP/C.LDSP, these encodings can be used with the zero register, so checking that the rs2 field is non-zero is unnecessary. Additionally, the previous check was incorrect since it was checking the immediate field of the instruction instead of the rs2 field. Signed-off-by: Amanieu d'Antras <amanieu@gmail.com> Reviewed-by: Anup Patel <anup@brainfault.org>
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1 changed files with 2 additions and 4 deletions
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@ -211,16 +211,14 @@ int sbi_misaligned_store_handler(ulong addr, ulong tval2, ulong tinst,
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} else if ((insn & INSN_MASK_C_SD) == INSN_MATCH_C_SD) {
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len = 8;
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val.data_ulong = GET_RS2S(insn, regs);
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} else if ((insn & INSN_MASK_C_SDSP) == INSN_MATCH_C_SDSP &&
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((insn >> SH_RD) & 0x1f)) {
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} else if ((insn & INSN_MASK_C_SDSP) == INSN_MATCH_C_SDSP) {
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len = 8;
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val.data_ulong = GET_RS2C(insn, regs);
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#endif
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} else if ((insn & INSN_MASK_C_SW) == INSN_MATCH_C_SW) {
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len = 4;
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val.data_ulong = GET_RS2S(insn, regs);
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} else if ((insn & INSN_MASK_C_SWSP) == INSN_MATCH_C_SWSP &&
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((insn >> SH_RD) & 0x1f)) {
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} else if ((insn & INSN_MASK_C_SWSP) == INSN_MATCH_C_SWSP) {
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len = 4;
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val.data_ulong = GET_RS2C(insn, regs);
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#ifdef __riscv_flen
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