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platform: generic: andes/renesas: Add SBI EXT to check for enabling IOCP errata
I/O Coherence Port (IOCP) provides an AXI interface for connecting external non-caching masters, such as DMA controllers. The accesses from IOCP are coherent with D-Caches and L2 Cache. IOCP is a specification option and is disabled on the Renesas RZ/Five SoC (which is based on Andes AX45MP core) due to this reason IP blocks using DMA will fail. As a workaround for SoCs with IOCP disabled CMO needs to be handled by software. Firstly OpenSBI configures the memory region as "Memory, Non-cacheable, Bufferable" and passes this region as a global shared dma pool as a DT node. With DMA_GLOBAL_POOL enabled all DMA allocations happen from this region and synchronization callbacks are implemented to synchronize when doing DMA transactions. SBI_EXT_ANDES_IOCP_SW_WORKAROUND checks if the IOCP errata should be applied to handle cache management. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Anup Patel <anup@brainfault.org> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
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7 changed files with 95 additions and 2 deletions
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@ -36,6 +36,7 @@ config PLATFORM_ANDES_AE350
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config PLATFORM_RENESAS_RZFIVE
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bool "Renesas RZ/Five support"
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select ANDES45_PMA
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select ANDES_SBI
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default n
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config PLATFORM_SIFIVE_FU540
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@ -3,3 +3,7 @@
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config ANDES45_PMA
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bool "Andes PMA support"
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default n
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config ANDES_SBI
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bool "Andes SBI support"
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default n
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51
platform/generic/andes/andes_sbi.c
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51
platform/generic/andes/andes_sbi.c
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@ -0,0 +1,51 @@
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// SPDX-License-Identifier: BSD-2-Clause
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/*
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* Copyright (C) 2023 Renesas Electronics Corp.
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*
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*/
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#include <andes/andes45.h>
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#include <andes/andes_sbi.h>
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#include <sbi/riscv_asm.h>
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#include <sbi/sbi_error.h>
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enum sbi_ext_andes_fid {
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SBI_EXT_ANDES_FID0 = 0, /* Reserved for future use */
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SBI_EXT_ANDES_IOCP_SW_WORKAROUND,
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};
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static bool andes45_cache_controllable(void)
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{
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return (((csr_read(CSR_MICM_CFG) & MICM_CFG_ISZ_MASK) ||
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(csr_read(CSR_MDCM_CFG) & MDCM_CFG_DSZ_MASK)) &&
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(csr_read(CSR_MMSC_CFG) & MMSC_CFG_CCTLCSR_MASK) &&
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(csr_read(CSR_MCACHE_CTL) & MCACHE_CTL_CCTL_SUEN_MASK) &&
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misa_extension('U'));
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}
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static bool andes45_iocp_disabled(void)
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{
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return (csr_read(CSR_MMSC_CFG) & MMSC_IOCP_MASK) ? false : true;
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}
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static bool andes45_apply_iocp_sw_workaround(void)
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{
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return andes45_cache_controllable() & andes45_iocp_disabled();
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}
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int andes_sbi_vendor_ext_provider(long funcid,
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const struct sbi_trap_regs *regs,
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unsigned long *out_value,
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struct sbi_trap_info *out_trap,
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const struct fdt_match *match)
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{
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switch (funcid) {
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case SBI_EXT_ANDES_IOCP_SW_WORKAROUND:
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*out_value = andes45_apply_iocp_sw_workaround();
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break;
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default:
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return SBI_EINVAL;
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}
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return 0;
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}
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@ -6,3 +6,4 @@ carray-platform_override_modules-$(CONFIG_PLATFORM_ANDES_AE350) += andes_ae350
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platform-objs-$(CONFIG_PLATFORM_ANDES_AE350) += andes/ae350.o andes/sleep.o
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platform-objs-$(CONFIG_ANDES45_PMA) += andes/andes45-pma.o
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platform-objs-$(CONFIG_ANDES_SBI) += andes/andes_sbi.o
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@ -4,7 +4,26 @@
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#define CSR_MARCHID_MICROID 0xfff
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/* Memory and Miscellaneous Registers */
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#define CSR_MCACHE_CTL 0x7ca
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#define CSR_MCCTLCOMMAND 0x7cc
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#define CSR_MCACHE_CTL 0x7ca
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#define CSR_MCCTLCOMMAND 0x7cc
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/* Configuration Control & Status Registers */
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#define CSR_MICM_CFG 0xfc0
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#define CSR_MDCM_CFG 0xfc1
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#define CSR_MMSC_CFG 0xfc2
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#define MICM_CFG_ISZ_OFFSET 6
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#define MICM_CFG_ISZ_MASK (0x7 << MICM_CFG_ISZ_OFFSET)
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#define MDCM_CFG_DSZ_OFFSET 6
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#define MDCM_CFG_DSZ_MASK (0x7 << MDCM_CFG_DSZ_OFFSET)
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#define MMSC_CFG_CCTLCSR_OFFSET 16
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#define MMSC_CFG_CCTLCSR_MASK (0x1 << MMSC_CFG_CCTLCSR_OFFSET)
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#define MMSC_IOCP_OFFSET 47
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#define MMSC_IOCP_MASK (0x1ULL << MMSC_IOCP_OFFSET)
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#define MCACHE_CTL_CCTL_SUEN_OFFSET 8
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#define MCACHE_CTL_CCTL_SUEN_MASK (0x1 << MCACHE_CTL_CCTL_SUEN_OFFSET)
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#endif /* _RISCV_ANDES45_H */
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15
platform/generic/include/andes/andes_sbi.h
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15
platform/generic/include/andes/andes_sbi.h
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@ -0,0 +1,15 @@
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// SPDX-License-Identifier: BSD-2-Clause
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#ifndef _RISCV_ANDES_SBI_H
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#define _RISCV_ANDES_SBI_H
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#include <sbi/sbi_trap.h>
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#include <sbi_utils/fdt/fdt_helper.h>
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int andes_sbi_vendor_ext_provider(long funcid,
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const struct sbi_trap_regs *regs,
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unsigned long *out_value,
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struct sbi_trap_info *out_trap,
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const struct fdt_match *match);
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#endif /* _RISCV_ANDES_SBI_H */
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@ -5,6 +5,7 @@
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*/
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#include <andes/andes45_pma.h>
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#include <andes/andes_sbi.h>
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#include <platform_override.h>
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#include <sbi/sbi_domain.h>
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#include <sbi_utils/fdt/fdt_helper.h>
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@ -55,4 +56,5 @@ const struct platform_override renesas_rzfive = {
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.match_table = renesas_rzfive_match,
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.early_init = renesas_rzfive_early_init,
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.final_init = renesas_rzfive_final_init,
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.vendor_ext_provider = andes_sbi_vendor_ext_provider,
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};
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