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Merge pull request #1 from riscv/atish_fix_1
Various fixes for unleashed board
This commit is contained in:
Anup Patel
GitHub
commit
f02926c896
8 changed files with 79 additions and 25 deletions
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@ -122,7 +122,10 @@ _start_warm:
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csrw mie, zero
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csrw mip, zero
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/* HART ID should be within expected limit */
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/* set MSIE bit to receive IPI */
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li a2, MIP_MSIP
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csrw mie, a2
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/* HART ID should be withing expected limit */
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csrr a6, mhartid
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li a5, PLAT_HART_COUNT
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bge a6, a5, _start_hang
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@ -36,6 +36,6 @@ struct sbi_scratch *sbi_hart_id_to_scratch(struct sbi_scratch *scratch,
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void sbi_hart_wait_for_coldboot(struct sbi_scratch *scratch, u32 hartid);
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void sbi_hart_wake_coldboot_harts(struct sbi_scratch *scratch);
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void sbi_hart_wake_coldboot_harts(struct sbi_scratch *scratch, u32 hartid);
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#endif
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@ -31,6 +31,8 @@ char sbi_getc(void)
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void sbi_putc(char ch)
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{
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if (ch == '\n')
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sbi_platform_console_putc(console_plat, '\r');
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sbi_platform_console_putc(console_plat, ch);
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}
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@ -291,7 +293,12 @@ static int print(char **out, u32 *out_len, const char *format, va_list args)
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}
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continue;
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} else if (*format == 'l') {
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if (*(format + 1) == 'x') {
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if (*(format + 1) == 'u') {
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format += 1;
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pc += printi(out, out_len,
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va_arg(args, unsigned long),
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10, 0, width, flags, 'a');
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} else if (*(format + 1) == 'x') {
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format += 1;
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pc += printi(out, out_len,
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va_arg(args, unsigned long),
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@ -264,31 +264,34 @@ struct sbi_scratch *sbi_hart_id_to_scratch(struct sbi_scratch *scratch,
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}
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#define NO_HOTPLUG_BITMAP_SIZE __riscv_xlen
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static spinlock_t coldboot_holding_pen_lock = SPIN_LOCK_INITIALIZER;
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static volatile unsigned long coldboot_holding_pen = 0;
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void sbi_hart_wait_for_coldboot(struct sbi_scratch *scratch, u32 hartid)
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{
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unsigned long done;
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unsigned long mipval;
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struct sbi_platform *plat = sbi_platform_ptr(scratch);
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sbi_printf("%s: In hartid = [%d]\n", __func__, hartid);
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if ((sbi_platform_hart_count(plat) <= hartid) ||
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(NO_HOTPLUG_BITMAP_SIZE <= hartid))
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sbi_hart_hang();
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do {
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wfi();
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mipval = csr_read(mip);
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/* Make sure the hart woke because of ipi */
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} while (!(mipval && MIP_MSIP) );
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while (1) {
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spin_lock(&coldboot_holding_pen_lock);
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done = coldboot_holding_pen;
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spin_unlock(&coldboot_holding_pen_lock);
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if (done)
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break;
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cpu_relax();
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}
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csr_clear(mip, MIP_MSIP);
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}
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void sbi_hart_wake_coldboot_harts(struct sbi_scratch *scratch)
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void sbi_hart_wake_coldboot_harts(struct sbi_scratch *scratch, u32 hartid)
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{
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spin_lock(&coldboot_holding_pen_lock);
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coldboot_holding_pen = 1;
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spin_unlock(&coldboot_holding_pen_lock);
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struct sbi_platform *plat = sbi_platform_ptr(scratch);
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int max_hart = sbi_platform_hart_count(plat);
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for(int i = 0; i < max_hart ; i++) {
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/* send an IPI to every other hart */
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if (i != hartid)
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sbi_platform_ipi_inject(plat, i, hartid);
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}
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}
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@ -96,7 +96,7 @@ static void __attribute__((noreturn)) init_coldboot(struct sbi_scratch *scratch,
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sbi_hart_mark_available(hartid);
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if (!sbi_platform_has_hart_hotplug(plat))
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sbi_hart_wake_coldboot_harts(scratch);
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sbi_hart_wake_coldboot_harts(scratch, hartid);
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sbi_hart_boot_next(hartid, scratch->next_arg1,
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scratch->next_addr, scratch->next_mode);
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@ -8,6 +8,7 @@
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*/
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#include <sbi/riscv_io.h>
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#include <sbi/sbi_console.h>
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#include <plat/serial/sifive-uart.h>
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#define UART_REG_TXFIFO 0
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@ -28,6 +29,29 @@ static volatile void *uart_base;
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static u32 uart_in_freq;
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static u32 uart_baudrate;
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/**
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* Find minimum divisor divides in_freq to max_target_hz;
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* Based on uart driver n SiFive FSBL.
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*
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* f_baud = f_in / (div + 1) => div = (f_in / f_baud) - 1
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* The nearest integer solution requires rounding up as to not exceed max_target_hz.
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* div = ceil(f_in / f_baud) - 1
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* = floor((f_in - 1 + f_baud) / f_baud) - 1
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* This should not overflow as long as (f_in - 1 + f_baud) does not exceed
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* 2^32 - 1, which is unlikely since we represent frequencies in kHz.
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*/
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static inline unsigned int uart_min_clk_divisor(uint64_t in_freq,
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uint64_t max_target_hz)
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{
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uint64_t quotient = (in_freq + max_target_hz - 1) / (max_target_hz);
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// Avoid underflow
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if (quotient == 0) {
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return 0;
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} else {
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return quotient - 1;
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}
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}
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static u32 get_reg(u32 num)
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{
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return readl(uart_base + (num * 0x4));
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@ -61,7 +85,7 @@ int sifive_uart_init(unsigned long base,
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uart_baudrate = baudrate;
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/* Configure baudrate */
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set_reg(UART_REG_DIV, (in_freq / baudrate) - 1);
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set_reg(UART_REG_DIV, uart_min_clk_divisor(in_freq, baudrate));
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/* Disable interrupts */
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set_reg(UART_REG_IE, 0);
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/* Enable TX */
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@ -9,7 +9,7 @@
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# Essential defines required by SBI platform
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plat-cppflags-y = -DPLAT_NAME="SiFive HiFive U540"
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plat-cppflags-y+= -DPLAT_HART_COUNT=1
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plat-cppflags-y+= -DPLAT_HART_COUNT=5
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plat-cppflags-y+= -DPLAT_HART_STACK_SIZE=8192
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# Compiler flags
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@ -10,12 +10,12 @@
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#include <sbi/riscv_encoding.h>
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#include <sbi/sbi_const.h>
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#include <sbi/sbi_platform.h>
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#include <sbi/riscv_io.h>
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#include <plat/irqchip/plic.h>
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#include <plat/serial/sifive-uart.h>
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#include <plat/sys/clint.h>
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#define SIFIVE_U_SYS_CLK 1000000000
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#define SIFIVE_U_PERIPH_CLK (SIFIVE_U_SYS_CLK / 2)
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#define SIFIVE_U_CLINT_ADDR 0x2000000
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@ -23,8 +23,15 @@
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#define SIFIVE_U_PLIC_NUM_SOURCES 0x35
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#define SIFIVE_U_PLIC_NUM_PRIORITIES 7
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#define SIFIVE_U_UART0_ADDR 0x10013000
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#define SIFIVE_U_UART1_ADDR 0x10023000
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#define SIFIVE_U_UART0_ADDR 0x10010000
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#define SIFIVE_U_UART1_ADDR 0x10011000
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#define SIFIVE_UART_BAUDRATE 115200
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/* PRCI clock related macros */
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//TODO: Do we need a separate driver for this ?
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#define SIFIVE_PRCI_BASE_ADDR 0x10000000
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#define SIFIVE_PRCI_CLKMUXSTATUSREG 0x002C
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#define SIFIVE_PRCI_CLKMUX_STATUS_TLCLKSEL (0x1 << 1)
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static int sifive_u_cold_final_init(void)
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{
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@ -57,8 +64,18 @@ static int sifive_u_pmp_region_info(u32 target_hart, u32 index,
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static int sifive_u_console_init(void)
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{
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unsigned long peri_in_freq;
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if (readl((volatile void *)SIFIVE_PRCI_BASE_ADDR +
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SIFIVE_PRCI_CLKMUXSTATUSREG) &
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SIFIVE_PRCI_CLKMUX_STATUS_TLCLKSEL){
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peri_in_freq = SIFIVE_U_SYS_CLK;
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} else {
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peri_in_freq = SIFIVE_U_SYS_CLK / 2;
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}
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return sifive_uart_init(SIFIVE_U_UART0_ADDR,
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SIFIVE_U_PERIPH_CLK, 115200);
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peri_in_freq, SIFIVE_UART_BAUDRATE);
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}
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static int sifive_u_cold_irqchip_init(void)
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