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platform: Add OpenPiton platform support
OpenPiton is a research platform from Princeton University [1]. "OpenPiton is the world's first open source, general purpose, multithreaded manycore processor. It is a tiled manycore framework scalable from one to 1/2 billion cores." Add OpenSBI support for OpenPiton. As it is based on ariane core, it reuses the platform code from arine project. [1]. https://github.com/PrincetonUniversity/openpiton Signed-off-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
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33
docs/platform/fpga-openpiton.md
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33
docs/platform/fpga-openpiton.md
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OpenPiton FPGA SoC Platform
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========================
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OpenPiton is the world's first open source, general purpose, multithreaded
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manycore processor. It is a tiled manycore framework scalable from one to
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1/2 billion cores. Currently, OpenPiton supports the 64bit Ariane RISC-V
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processor from ETH Zurich. To this end, Ariane has been equipped with a
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different L1 cache subsystem that follows a write-through protocol and that has
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support for cache invalidations and atomics.
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To build platform specific library and firmwares, provide the
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*PLATFORM=fpga/openpiton* parameter to the top level `make` command.
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Platform Options
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----------------
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The *OpenPiton* platform does not have any platform-specific options.
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Building Ariane FPGA Platform
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-----------------------------
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**Linux Kernel Payload**
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```
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make PLATFORM=fpga/openpiton FW_PAYLOAD_PATH=<linux_build_directory>/arch/riscv/boot/Image
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```
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Booting Ariane FPGA Platform
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----------------------------
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**Linux Kernel Payload**
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As Linux kernel image is embedded in the OpenSBI firmware binary, Ariane will
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directly boot into Linux directly after powered on.
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@ -25,6 +25,9 @@ OpenSBI currently supports the following virtual and hardware platforms:
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* **Spike**: Platform support for the Spike emulator.
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* **OpenPiton FPGA SoC**: Platform support OpenPiton research platform based on
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ariane core.
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The code for these supported platforms can be used as example to implement
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support for other platforms. The *platform/template* directory also provides
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template files for implementing support for a new platform. The *object.mk*,
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@ -37,3 +40,4 @@ facilitate the implementation.
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[andes_ae350.md]: andes-ae350.md
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[thead-c910.md]: thead-c910.md
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[spike.md]: spike.md
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[fpga_openpiton.md]: fpga_openpiton.md
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35
platform/fpga/openpiton/config.mk
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platform/fpga/openpiton/config.mk
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#
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# SPDX-License-Identifier: BSD-2-Clause
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#
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# Copyright (c) 2020 Western Digital Corporation or its affiliates.
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#
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#for more infos, check out /platform/template/config.mk
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PLATFORM_RISCV_XLEN = 64
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# Blobs to build
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FW_TEXT_START=0x80000000
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FW_JUMP=n
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ifeq ($(PLATFORM_RISCV_XLEN), 32)
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# This needs to be 4MB aligned for 32-bit support
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FW_JUMP_ADDR=0x80400000
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else
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# This needs to be 2MB aligned for 64-bit support
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FW_JUMP_ADDR=0x80200000
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endif
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FW_JUMP_FDT_ADDR=0x82200000
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# Firmware with payload configuration.
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FW_PAYLOAD=y
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ifeq ($(PLATFORM_RISCV_XLEN), 32)
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# This needs to be 4MB aligned for 32-bit support
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FW_PAYLOAD_OFFSET=0x400000
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else
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# This needs to be 2MB aligned for 64-bit support
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FW_PAYLOAD_OFFSET=0x200000
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endif
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FW_PAYLOAD_FDT_ADDR=0x82200000
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FW_PAYLOAD_ALIGN=0x1000
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7
platform/fpga/openpiton/objects.mk
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7
platform/fpga/openpiton/objects.mk
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#
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# SPDX-License-Identifier: BSD-2-Clause
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#
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# Copyright (c) 2020 Western Digital Corporation or its affiliates.
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#
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platform-objs-y += platform.o
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200
platform/fpga/openpiton/platform.c
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platform/fpga/openpiton/platform.c
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// SPDX-License-Identifier: BSD-2-Clause
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/*
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* Copyright (c) 2020 Western Digital Corporation or its affiliates.
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*/
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#include <sbi/riscv_asm.h>
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#include <sbi/riscv_encoding.h>
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#include <sbi/riscv_io.h>
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#include <sbi/sbi_console.h>
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#include <sbi/sbi_const.h>
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#include <sbi/sbi_hart.h>
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#include <sbi/sbi_platform.h>
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#include <sbi_utils/fdt/fdt_helper.h>
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#include <sbi_utils/irqchip/plic.h>
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#include <sbi_utils/serial/uart8250.h>
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#include <sbi_utils/sys/clint.h>
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#define OPENPITON_UART_ADDR 0xfff0c2c000
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#define OPENPITON_UART_FREQ 60000000
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#define OPENPITON_UART_BAUDRATE 115200
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#define OPENPITON_UART_REG_SHIFT 0
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#define OPENPITON_UART_REG_WIDTH 1
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#define OPENPITON_PLIC_ADDR 0xfff1100000
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#define OPENPITON_PLIC_NUM_SOURCES 2
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#define OPENPITON_HART_COUNT 3
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#define OPENPITON_CLINT_ADDR 0xfff1020000
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#define SBI_OPENPITON_FEATURES \
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(SBI_PLATFORM_HAS_TIMER_VALUE | \
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SBI_PLATFORM_HAS_SCOUNTEREN | \
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SBI_PLATFORM_HAS_MCOUNTEREN | \
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SBI_PLATFORM_HAS_MFAULTS_DELEGATION)
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/*
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* OpenPiton platform early initialization.
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*/
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static int openpiton_early_init(bool cold_boot)
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{
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/* For now nothing to do. */
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return 0;
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}
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/*
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* OpenPiton platform final initialization.
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*/
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static int openpiton_final_init(bool cold_boot)
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{
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void *fdt;
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if (!cold_boot)
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return 0;
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fdt = sbi_scratch_thishart_arg1_ptr();
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fdt_fixups(fdt);
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return 0;
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}
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/*
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* Initialize the openpiton console.
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*/
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static int openpiton_console_init(void)
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{
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return uart8250_init(OPENPITON_UART_ADDR,
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OPENPITON_UART_FREQ,
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OPENPITON_UART_BAUDRATE,
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OPENPITON_UART_REG_SHIFT,
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OPENPITON_UART_REG_WIDTH);
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}
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static int plic_openpiton_warm_irqchip_init(u32 target_hart,
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int m_cntx_id, int s_cntx_id)
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{
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size_t i, ie_words = OPENPITON_PLIC_NUM_SOURCES / 32 + 1;
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if (target_hart >= OPENPITON_HART_COUNT)
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return -1;
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/* By default, enable all IRQs for M-mode of target HART */
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if (m_cntx_id > -1) {
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for (i = 0; i < ie_words; i++)
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plic_set_ie(m_cntx_id, i, 1);
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}
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/* Enable all IRQs for S-mode of target HART */
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if (s_cntx_id > -1) {
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for (i = 0; i < ie_words; i++)
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plic_set_ie(s_cntx_id, i, 1);
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}
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/* By default, enable M-mode threshold */
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if (m_cntx_id > -1)
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plic_set_thresh(m_cntx_id, 1);
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/* By default, disable S-mode threshold */
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if (s_cntx_id > -1)
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plic_set_thresh(s_cntx_id, 0);
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return 0;
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}
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/*
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* Initialize the openpiton interrupt controller for current HART.
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*/
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static int openpiton_irqchip_init(bool cold_boot)
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{
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u32 hartid = current_hartid();
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int ret;
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if (cold_boot) {
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ret = plic_cold_irqchip_init(OPENPITON_PLIC_ADDR,
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OPENPITON_PLIC_NUM_SOURCES,
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OPENPITON_HART_COUNT);
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if (ret)
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return ret;
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}
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return plic_openpiton_warm_irqchip_init(hartid,
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2 * hartid, 2 * hartid + 1);
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}
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/*
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* Initialize IPI for current HART.
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*/
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static int openpiton_ipi_init(bool cold_boot)
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{
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int ret;
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if (cold_boot) {
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ret = clint_cold_ipi_init(OPENPITON_CLINT_ADDR,
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OPENPITON_HART_COUNT);
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if (ret)
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return ret;
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}
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return clint_warm_ipi_init();
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}
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/*
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* Initialize openpiton timer for current HART.
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*/
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static int openpiton_timer_init(bool cold_boot)
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{
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int ret;
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if (cold_boot) {
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ret = clint_cold_timer_init(OPENPITON_CLINT_ADDR,
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OPENPITON_HART_COUNT, TRUE);
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if (ret)
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return ret;
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}
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return clint_warm_timer_init();
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}
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/*
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* Reboot the openpiton.
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*/
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static int openpiton_system_reboot(u32 type)
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{
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/* For now nothing to do. */
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sbi_printf("System reboot\n");
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return 0;
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}
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/*
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* Shutdown or poweroff the openpiton.
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*/
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static int openpiton_system_shutdown(u32 type)
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{
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/* For now nothing to do. */
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sbi_printf("System shutdown\n");
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return 0;
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}
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/*
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* Platform descriptor.
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*/
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const struct sbi_platform_operations platform_ops = {
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.early_init = openpiton_early_init,
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.final_init = openpiton_final_init,
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.console_init = openpiton_console_init,
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.console_putc = uart8250_putc,
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.console_getc = uart8250_getc,
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.irqchip_init = openpiton_irqchip_init,
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.ipi_init = openpiton_ipi_init,
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.ipi_send = clint_ipi_send,
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.ipi_clear = clint_ipi_clear,
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.timer_init = openpiton_timer_init,
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.timer_value = clint_timer_value,
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.timer_event_start = clint_timer_event_start,
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.timer_event_stop = clint_timer_event_stop,
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.system_reboot = openpiton_system_reboot,
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.system_shutdown = openpiton_system_shutdown
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};
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const struct sbi_platform platform = {
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.opensbi_version = OPENSBI_VERSION,
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.platform_version = SBI_PLATFORM_VERSION(0x0, 0x01),
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.name = "OPENPITON RISC-V",
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.features = SBI_OPENPITON_FEATURES,
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.hart_count = OPENPITON_HART_COUNT,
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.hart_stack_size = SBI_PLATFORM_DEFAULT_HART_STACK_SIZE,
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.platform_ops_addr = (unsigned long)&platform_ops
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};
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@ -93,6 +93,7 @@ case "${BUILD_RISCV_XLEN}" in
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BUILD_PLATFORM_SUBDIR+=("sifive/fu540")
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BUILD_PLATFORM_SUBDIR+=("kendryte/k210")
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BUILD_PLATFORM_SUBDIR+=("fpga/ariane")
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BUILD_PLATFORM_SUBDIR+=("fpga/openpiton")
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BUILD_PLATFORM_SUBDIR+=("andes/ae350")
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BUILD_PLATFORM_SUBDIR+=("thead/c910")
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BUILD_PLATFORM_SUBDIR+=("spike")
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