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c104c60912
This adds the support for ISA extension smcntrpmf. When some inhibit flags are set by a lower privilege mode for new CSRs added by smcntrpmf, OpenSBI sets the appropriate values correspondingly. Signed-off-by: Kaiwen Xue <kaiwenx@andrew.cmu.edu> Signed-off-by: Kaiwen Xue <kaiwenx@rivosinc.com> Reviewed-by: Anup Patel <anup@brainfault.org> Reviewed-by: Atish Patra <atishp@rivosinc.com>
404 lines
11 KiB
C
404 lines
11 KiB
C
/*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2019 Western Digital Corporation or its affiliates.
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*
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* Authors:
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* Anup Patel <anup.patel@wdc.com>
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*/
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#include <sbi/riscv_asm.h>
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#include <sbi/riscv_encoding.h>
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#include <sbi/sbi_error.h>
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#include <sbi/sbi_platform.h>
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#include <sbi/sbi_console.h>
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/* determine CPU extension, return non-zero support */
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int misa_extension_imp(char ext)
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{
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unsigned long misa = csr_read(CSR_MISA);
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if (misa) {
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if ('A' <= ext && ext <= 'Z')
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return misa & (1 << (ext - 'A'));
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if ('a' <= ext && ext <= 'z')
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return misa & (1 << (ext - 'a'));
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return 0;
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}
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return sbi_platform_misa_extension(sbi_platform_thishart_ptr(), ext);
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}
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int misa_xlen(void)
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{
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long r;
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if (csr_read(CSR_MISA) == 0)
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return sbi_platform_misa_xlen(sbi_platform_thishart_ptr());
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__asm__ __volatile__(
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"csrr t0, misa\n\t"
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"slti t1, t0, 0\n\t"
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"slli t1, t1, 1\n\t"
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"slli t0, t0, 1\n\t"
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"slti t0, t0, 0\n\t"
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"add %0, t0, t1"
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: "=r"(r)
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:
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: "t0", "t1");
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return r ? r : -1;
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}
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void misa_string(int xlen, char *out, unsigned int out_sz)
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{
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unsigned int i, pos = 0;
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const char valid_isa_order[] = "iemafdqclbjtpvnhkorwxyzg";
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if (!out)
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return;
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if (5 <= (out_sz - pos)) {
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out[pos++] = 'r';
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out[pos++] = 'v';
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switch (xlen) {
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case 1:
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out[pos++] = '3';
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out[pos++] = '2';
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break;
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case 2:
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out[pos++] = '6';
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out[pos++] = '4';
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break;
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case 3:
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out[pos++] = '1';
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out[pos++] = '2';
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out[pos++] = '8';
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break;
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default:
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sbi_panic("%s: Unknown misa.MXL encoding %d",
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__func__, xlen);
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return;
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}
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}
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for (i = 0; i < array_size(valid_isa_order) && (pos < out_sz); i++) {
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if (misa_extension_imp(valid_isa_order[i]))
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out[pos++] = valid_isa_order[i];
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}
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if (pos < out_sz)
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out[pos++] = '\0';
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}
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unsigned long csr_read_num(int csr_num)
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{
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#define switchcase_csr_read(__csr_num, __val) \
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case __csr_num: \
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__val = csr_read(__csr_num); \
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break;
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#define switchcase_csr_read_2(__csr_num, __val) \
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switchcase_csr_read(__csr_num + 0, __val) \
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switchcase_csr_read(__csr_num + 1, __val)
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#define switchcase_csr_read_4(__csr_num, __val) \
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switchcase_csr_read_2(__csr_num + 0, __val) \
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switchcase_csr_read_2(__csr_num + 2, __val)
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#define switchcase_csr_read_8(__csr_num, __val) \
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switchcase_csr_read_4(__csr_num + 0, __val) \
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switchcase_csr_read_4(__csr_num + 4, __val)
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#define switchcase_csr_read_16(__csr_num, __val) \
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switchcase_csr_read_8(__csr_num + 0, __val) \
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switchcase_csr_read_8(__csr_num + 8, __val)
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#define switchcase_csr_read_32(__csr_num, __val) \
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switchcase_csr_read_16(__csr_num + 0, __val) \
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switchcase_csr_read_16(__csr_num + 16, __val)
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#define switchcase_csr_read_64(__csr_num, __val) \
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switchcase_csr_read_32(__csr_num + 0, __val) \
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switchcase_csr_read_32(__csr_num + 32, __val)
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unsigned long ret = 0;
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switch (csr_num) {
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switchcase_csr_read_16(CSR_PMPCFG0, ret)
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switchcase_csr_read_64(CSR_PMPADDR0, ret)
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switchcase_csr_read(CSR_MCYCLE, ret)
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switchcase_csr_read(CSR_MINSTRET, ret)
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switchcase_csr_read(CSR_MHPMCOUNTER3, ret)
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switchcase_csr_read_4(CSR_MHPMCOUNTER4, ret)
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switchcase_csr_read_8(CSR_MHPMCOUNTER8, ret)
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switchcase_csr_read_16(CSR_MHPMCOUNTER16, ret)
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switchcase_csr_read(CSR_MCOUNTINHIBIT, ret)
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switchcase_csr_read(CSR_MCYCLECFG, ret)
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switchcase_csr_read(CSR_MINSTRETCFG, ret)
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switchcase_csr_read(CSR_MHPMEVENT3, ret)
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switchcase_csr_read_4(CSR_MHPMEVENT4, ret)
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switchcase_csr_read_8(CSR_MHPMEVENT8, ret)
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switchcase_csr_read_16(CSR_MHPMEVENT16, ret)
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#if __riscv_xlen == 32
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switchcase_csr_read(CSR_MCYCLEH, ret)
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switchcase_csr_read(CSR_MINSTRETH, ret)
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switchcase_csr_read(CSR_MHPMCOUNTER3H, ret)
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switchcase_csr_read_4(CSR_MHPMCOUNTER4H, ret)
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switchcase_csr_read_8(CSR_MHPMCOUNTER8H, ret)
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switchcase_csr_read_16(CSR_MHPMCOUNTER16H, ret)
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/**
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* The CSR range M[CYCLE, INSTRET]CFGH are available only if smcntrpmf
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* extension is present. The caller must ensure that.
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*/
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switchcase_csr_read(CSR_MCYCLECFGH, ret)
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switchcase_csr_read(CSR_MINSTRETCFGH, ret)
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/**
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* The CSR range MHPMEVENT[3-16]H are available only if sscofpmf
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* extension is present. The caller must ensure that.
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*/
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switchcase_csr_read(CSR_MHPMEVENT3H, ret)
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switchcase_csr_read_4(CSR_MHPMEVENT4H, ret)
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switchcase_csr_read_8(CSR_MHPMEVENT8H, ret)
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switchcase_csr_read_16(CSR_MHPMEVENT16H, ret)
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#endif
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default:
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sbi_panic("%s: Unknown CSR %#x", __func__, csr_num);
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break;
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}
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return ret;
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#undef switchcase_csr_read_64
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#undef switchcase_csr_read_32
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#undef switchcase_csr_read_16
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#undef switchcase_csr_read_8
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#undef switchcase_csr_read_4
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#undef switchcase_csr_read_2
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#undef switchcase_csr_read
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}
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void csr_write_num(int csr_num, unsigned long val)
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{
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#define switchcase_csr_write(__csr_num, __val) \
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case __csr_num: \
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csr_write(__csr_num, __val); \
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break;
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#define switchcase_csr_write_2(__csr_num, __val) \
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switchcase_csr_write(__csr_num + 0, __val) \
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switchcase_csr_write(__csr_num + 1, __val)
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#define switchcase_csr_write_4(__csr_num, __val) \
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switchcase_csr_write_2(__csr_num + 0, __val) \
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switchcase_csr_write_2(__csr_num + 2, __val)
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#define switchcase_csr_write_8(__csr_num, __val) \
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switchcase_csr_write_4(__csr_num + 0, __val) \
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switchcase_csr_write_4(__csr_num + 4, __val)
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#define switchcase_csr_write_16(__csr_num, __val) \
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switchcase_csr_write_8(__csr_num + 0, __val) \
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switchcase_csr_write_8(__csr_num + 8, __val)
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#define switchcase_csr_write_32(__csr_num, __val) \
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switchcase_csr_write_16(__csr_num + 0, __val) \
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switchcase_csr_write_16(__csr_num + 16, __val)
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#define switchcase_csr_write_64(__csr_num, __val) \
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switchcase_csr_write_32(__csr_num + 0, __val) \
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switchcase_csr_write_32(__csr_num + 32, __val)
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switch (csr_num) {
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switchcase_csr_write_16(CSR_PMPCFG0, val)
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switchcase_csr_write_64(CSR_PMPADDR0, val)
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switchcase_csr_write(CSR_MCYCLE, val)
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switchcase_csr_write(CSR_MINSTRET, val)
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switchcase_csr_write(CSR_MHPMCOUNTER3, val)
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switchcase_csr_write_4(CSR_MHPMCOUNTER4, val)
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switchcase_csr_write_8(CSR_MHPMCOUNTER8, val)
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switchcase_csr_write_16(CSR_MHPMCOUNTER16, val)
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#if __riscv_xlen == 32
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switchcase_csr_write(CSR_MCYCLEH, val)
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switchcase_csr_write(CSR_MINSTRETH, val)
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switchcase_csr_write(CSR_MHPMCOUNTER3H, val)
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switchcase_csr_write_4(CSR_MHPMCOUNTER4H, val)
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switchcase_csr_write_8(CSR_MHPMCOUNTER8H, val)
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switchcase_csr_write_16(CSR_MHPMCOUNTER16H, val)
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switchcase_csr_write(CSR_MCYCLECFGH, val)
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switchcase_csr_write(CSR_MINSTRETCFGH, val)
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switchcase_csr_write(CSR_MHPMEVENT3H, val)
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switchcase_csr_write_4(CSR_MHPMEVENT4H, val)
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switchcase_csr_write_8(CSR_MHPMEVENT8H, val)
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switchcase_csr_write_16(CSR_MHPMEVENT16H, val)
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#endif
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switchcase_csr_write(CSR_MCOUNTINHIBIT, val)
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switchcase_csr_write(CSR_MCYCLECFG, val)
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switchcase_csr_write(CSR_MINSTRETCFG, val)
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switchcase_csr_write(CSR_MHPMEVENT3, val)
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switchcase_csr_write_4(CSR_MHPMEVENT4, val)
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switchcase_csr_write_8(CSR_MHPMEVENT8, val)
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switchcase_csr_write_16(CSR_MHPMEVENT16, val)
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default:
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sbi_panic("%s: Unknown CSR %#x", __func__, csr_num);
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break;
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}
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#undef switchcase_csr_write_64
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#undef switchcase_csr_write_32
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#undef switchcase_csr_write_16
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#undef switchcase_csr_write_8
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#undef switchcase_csr_write_4
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#undef switchcase_csr_write_2
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#undef switchcase_csr_write
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}
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static unsigned long ctz(unsigned long x)
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{
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unsigned long ret = 0;
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if (x == 0)
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return 8 * sizeof(x);
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while (!(x & 1UL)) {
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ret++;
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x = x >> 1;
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}
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return ret;
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}
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int pmp_disable(unsigned int n)
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{
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int pmpcfg_csr, pmpcfg_shift;
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unsigned long cfgmask, pmpcfg;
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if (n >= PMP_COUNT)
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return SBI_EINVAL;
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#if __riscv_xlen == 32
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pmpcfg_csr = CSR_PMPCFG0 + (n >> 2);
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pmpcfg_shift = (n & 3) << 3;
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#elif __riscv_xlen == 64
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pmpcfg_csr = (CSR_PMPCFG0 + (n >> 2)) & ~1;
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pmpcfg_shift = (n & 7) << 3;
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#else
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# error "Unexpected __riscv_xlen"
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#endif
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/* Clear the address matching bits to disable the pmp entry */
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cfgmask = ~(0xffUL << pmpcfg_shift);
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pmpcfg = (csr_read_num(pmpcfg_csr) & cfgmask);
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csr_write_num(pmpcfg_csr, pmpcfg);
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return SBI_OK;
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}
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int is_pmp_entry_mapped(unsigned long entry)
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{
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unsigned long prot;
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unsigned long addr;
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unsigned long log2len;
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pmp_get(entry, &prot, &addr, &log2len);
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/* If address matching bits are non-zero, the entry is enable */
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if (prot & PMP_A)
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return true;
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return false;
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}
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int pmp_set(unsigned int n, unsigned long prot, unsigned long addr,
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unsigned long log2len)
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{
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int pmpcfg_csr, pmpcfg_shift, pmpaddr_csr;
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unsigned long cfgmask, pmpcfg;
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unsigned long addrmask, pmpaddr;
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/* check parameters */
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if (n >= PMP_COUNT || log2len > __riscv_xlen || log2len < PMP_SHIFT)
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return SBI_EINVAL;
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/* calculate PMP register and offset */
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#if __riscv_xlen == 32
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pmpcfg_csr = CSR_PMPCFG0 + (n >> 2);
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pmpcfg_shift = (n & 3) << 3;
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#elif __riscv_xlen == 64
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pmpcfg_csr = (CSR_PMPCFG0 + (n >> 2)) & ~1;
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pmpcfg_shift = (n & 7) << 3;
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#else
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# error "Unexpected __riscv_xlen"
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#endif
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pmpaddr_csr = CSR_PMPADDR0 + n;
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/* encode PMP config */
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prot &= ~PMP_A;
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prot |= (log2len == PMP_SHIFT) ? PMP_A_NA4 : PMP_A_NAPOT;
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cfgmask = ~(0xffUL << pmpcfg_shift);
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pmpcfg = (csr_read_num(pmpcfg_csr) & cfgmask);
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pmpcfg |= ((prot << pmpcfg_shift) & ~cfgmask);
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/* encode PMP address */
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if (log2len == PMP_SHIFT) {
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pmpaddr = (addr >> PMP_SHIFT);
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} else {
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if (log2len == __riscv_xlen) {
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pmpaddr = -1UL;
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} else {
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addrmask = (1UL << (log2len - PMP_SHIFT)) - 1;
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pmpaddr = ((addr >> PMP_SHIFT) & ~addrmask);
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pmpaddr |= (addrmask >> 1);
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}
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}
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/* write csrs */
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csr_write_num(pmpaddr_csr, pmpaddr);
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csr_write_num(pmpcfg_csr, pmpcfg);
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return 0;
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}
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int pmp_get(unsigned int n, unsigned long *prot_out, unsigned long *addr_out,
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unsigned long *log2len)
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{
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int pmpcfg_csr, pmpcfg_shift, pmpaddr_csr;
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unsigned long cfgmask, pmpcfg, prot;
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unsigned long t1, addr, len;
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/* check parameters */
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if (n >= PMP_COUNT || !prot_out || !addr_out || !log2len)
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return SBI_EINVAL;
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*prot_out = *addr_out = *log2len = 0;
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/* calculate PMP register and offset */
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#if __riscv_xlen == 32
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pmpcfg_csr = CSR_PMPCFG0 + (n >> 2);
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pmpcfg_shift = (n & 3) << 3;
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#elif __riscv_xlen == 64
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pmpcfg_csr = (CSR_PMPCFG0 + (n >> 2)) & ~1;
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pmpcfg_shift = (n & 7) << 3;
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#else
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# error "Unexpected __riscv_xlen"
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#endif
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pmpaddr_csr = CSR_PMPADDR0 + n;
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/* decode PMP config */
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cfgmask = (0xffUL << pmpcfg_shift);
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pmpcfg = csr_read_num(pmpcfg_csr) & cfgmask;
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prot = pmpcfg >> pmpcfg_shift;
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/* decode PMP address */
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if ((prot & PMP_A) == PMP_A_NAPOT) {
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addr = csr_read_num(pmpaddr_csr);
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if (addr == -1UL) {
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addr = 0;
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len = __riscv_xlen;
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} else {
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t1 = ctz(~addr);
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addr = (addr & ~((1UL << t1) - 1)) << PMP_SHIFT;
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len = (t1 + PMP_SHIFT + 1);
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}
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} else {
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addr = csr_read_num(pmpaddr_csr) << PMP_SHIFT;
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len = PMP_SHIFT;
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}
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/* return details */
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*prot_out = prot;
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*addr_out = addr;
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*log2len = len;
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return 0;
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}
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