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013ba4ef3d
The parameter passed to HFENCE.GVMA instruction in rs1 register
is guest physical address right shifted by 2 (i.e. divided by 4).
Unfortunately, we overlooked the semantics of rs1 registers for
HFENCE.GVMA instruction and never right shifted guest physical
address by 2. This issue did not manifest for hypervisors till
now because all H-extension implementations (such as QEMU, Spike,
Rocket Core FPGA, etc) we tried till now were conservatively
flushing everything upon any HFENCE.GVMA instruction.
This patch fixes GPA passed to __sbi_hfence_gvma_vmid_gpa()
and __sbi_hfence_gvma_gpa() functions.
Fixes: 331ff6a162 ("lib: Support stage1 and stage2 tlb flushing")
Reported-by: Ian Huang <ihuang@ventanamicro.com>
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Xiang W <wxjstz@126.com>
Reviewed-by: Dong Du <Dd_nirvana@sjtu.edu.cn>
135 lines
2.5 KiB
ArmAsm
135 lines
2.5 KiB
ArmAsm
/*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2019 Western Digital Corporation or its affiliates.
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*
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* Authors:
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* Anup Patel <anup.patel@wdc.com>
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* Atish Patra <anup.patel@wdc.com>
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*/
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/*
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* HFENCE.GVMA rs1, rs2
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* HFENCE.GVMA zero, rs2
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* HFENCE.GVMA rs1
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* HFENCE.GVMA
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*
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* rs1!=zero and rs2!=zero ==> HFENCE.GVMA rs1, rs2
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* rs1==zero and rs2!=zero ==> HFENCE.GVMA zero, rs2
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* rs1!=zero and rs2==zero ==> HFENCE.GVMA rs1
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* rs1==zero and rs2==zero ==> HFENCE.GVMA
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*
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* Instruction encoding of HFENCE.GVMA is:
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* 0110001 rs2(5) rs1(5) 000 00000 1110011
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*/
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.align 3
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.global __sbi_hfence_gvma_vmid_gpa
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__sbi_hfence_gvma_vmid_gpa:
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/*
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* rs1 = a0 (GPA >> 2)
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* rs2 = a1 (VMID)
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* HFENCE.GVMA a0, a1
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* 0110001 01011 01010 000 00000 1110011
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*/
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.word 0x62b50073
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ret
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.align 3
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.global __sbi_hfence_gvma_vmid
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__sbi_hfence_gvma_vmid:
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/*
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* rs1 = zero
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* rs2 = a0 (VMID)
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* HFENCE.GVMA zero, a0
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* 0110001 01010 00000 000 00000 1110011
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*/
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.word 0x62a00073
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ret
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.align 3
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.global __sbi_hfence_gvma_gpa
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__sbi_hfence_gvma_gpa:
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/*
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* rs1 = a0 (GPA >> 2)
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* rs2 = zero
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* HFENCE.GVMA a0
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* 0110001 00000 01010 000 00000 1110011
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*/
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.word 0x62050073
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ret
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.align 3
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.global __sbi_hfence_gvma_all
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__sbi_hfence_gvma_all:
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/*
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* rs1 = zero
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* rs2 = zero
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* HFENCE.GVMA
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* 0110001 00000 00000 000 00000 1110011
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*/
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.word 0x62000073
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ret
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/*
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* HFENCE.VVMA rs1, rs2
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* HFENCE.VVMA zero, rs2
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* HFENCE.VVMA rs1
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* HFENCE.VVMA
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*
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* rs1!=zero and rs2!=zero ==> HFENCE.VVMA rs1, rs2
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* rs1==zero and rs2!=zero ==> HFENCE.VVMA zero, rs2
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* rs1!=zero and rs2==zero ==> HFENCE.VVMA rs1
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* rs1==zero and rs2==zero ==> HFENCE.vVMA
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*
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* Instruction encoding of HFENCE.VVMA is:
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* 0010001 rs2(5) rs1(5) 000 00000 1110011
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*/
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.align 3
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.global __sbi_hfence_vvma_asid_va
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__sbi_hfence_vvma_asid_va:
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/*
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* rs1 = a0 (VA)
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* rs2 = a1 (ASID)
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* HFENCE.VVMA a0, a1
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* 0010001 01011 01010 000 00000 1110011
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*/
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.word 0x22b50073
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ret
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.align 3
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.global __sbi_hfence_vvma_asid
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__sbi_hfence_vvma_asid:
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/*
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* rs1 = zero
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* rs2 = a0 (ASID)
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* HFENCE.VVMA zero, a0
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* 0010001 01010 00000 000 00000 1110011
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*/
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.word 0x22a00073
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ret
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.align 3
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.global __sbi_hfence_vvma_va
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__sbi_hfence_vvma_va:
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/*
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* rs1 = a0 (VA)
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* rs2 = zero
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* HFENCE.VVMA zero, a0
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* 0010001 00000 01010 000 00000 1110011
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*/
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.word 0x22050073
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ret
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.align 3
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.global __sbi_hfence_vvma_all
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__sbi_hfence_vvma_all:
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/*
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* rs1 = zero
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* rs2 = zero
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* HFENCE.VVMA
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* 0010001 00000 00000 000 00000 1110011
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*/
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.word 0x22000073
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ret
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