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https://github.com/Fishwaldo/opensbi.git
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Currently, all non-coldboot HARTs busy spin in wait_for_coldboot() until the entire coldboot init sequence is completed. This means: 1) On QEMU, all non-coldboot HARTs will eat host CPU time and also slow down the coldboot HART until the entire coldboot init sequence is completed. 2) On real HW, all non-coldboot HARTs will consume more CPU power until the entire coldboot init sequence is completed. To address this, wake up all non-coldboot HARTs as early as possible in the coldboot init sequence. Signed-off-by: Anup Patel <apatel@ventanamicro.com>
623 lines
16 KiB
C
623 lines
16 KiB
C
/*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2019 Western Digital Corporation or its affiliates.
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*
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* Authors:
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* Anup Patel <anup.patel@wdc.com>
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*/
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#include <sbi/riscv_asm.h>
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#include <sbi/riscv_atomic.h>
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#include <sbi/riscv_barrier.h>
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#include <sbi/sbi_console.h>
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#include <sbi/sbi_cppc.h>
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#include <sbi/sbi_domain.h>
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#include <sbi/sbi_ecall.h>
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#include <sbi/sbi_hart.h>
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#include <sbi/sbi_hartmask.h>
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#include <sbi/sbi_heap.h>
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#include <sbi/sbi_hsm.h>
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#include <sbi/sbi_ipi.h>
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#include <sbi/sbi_irqchip.h>
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#include <sbi/sbi_platform.h>
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#include <sbi/sbi_pmu.h>
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#include <sbi/sbi_dbtr.h>
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#include <sbi/sbi_sse.h>
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#include <sbi/sbi_system.h>
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#include <sbi/sbi_string.h>
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#include <sbi/sbi_timer.h>
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#include <sbi/sbi_tlb.h>
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#include <sbi/sbi_version.h>
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#include <sbi/sbi_unit_test.h>
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#define BANNER \
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" ____ _____ ____ _____\n" \
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" / __ \\ / ____| _ \\_ _|\n" \
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" | | | |_ __ ___ _ __ | (___ | |_) || |\n" \
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" | | | | '_ \\ / _ \\ '_ \\ \\___ \\| _ < | |\n" \
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" | |__| | |_) | __/ | | |____) | |_) || |_\n" \
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" \\____/| .__/ \\___|_| |_|_____/|____/_____|\n" \
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" | |\n" \
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" |_|\n\n"
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static void sbi_boot_print_banner(struct sbi_scratch *scratch)
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{
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if (scratch->options & SBI_SCRATCH_NO_BOOT_PRINTS)
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return;
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#ifdef OPENSBI_VERSION_GIT
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sbi_printf("\nOpenSBI %s\n", OPENSBI_VERSION_GIT);
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#else
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sbi_printf("\nOpenSBI v%d.%d\n", OPENSBI_VERSION_MAJOR,
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OPENSBI_VERSION_MINOR);
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#endif
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#ifdef OPENSBI_BUILD_TIME_STAMP
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sbi_printf("Build time: %s\n", OPENSBI_BUILD_TIME_STAMP);
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#endif
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#ifdef OPENSBI_BUILD_COMPILER_VERSION
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sbi_printf("Build compiler: %s\n", OPENSBI_BUILD_COMPILER_VERSION);
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#endif
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sbi_printf(BANNER);
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}
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static void sbi_boot_print_general(struct sbi_scratch *scratch)
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{
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char str[128];
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const struct sbi_pmu_device *pdev;
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const struct sbi_hsm_device *hdev;
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const struct sbi_ipi_device *idev;
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const struct sbi_timer_device *tdev;
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const struct sbi_console_device *cdev;
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const struct sbi_system_reset_device *srdev;
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const struct sbi_system_suspend_device *susp_dev;
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const struct sbi_cppc_device *cppc_dev;
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const struct sbi_platform *plat = sbi_platform_ptr(scratch);
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if (scratch->options & SBI_SCRATCH_NO_BOOT_PRINTS)
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return;
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/* Platform details */
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sbi_printf("Platform Name : %s\n",
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sbi_platform_name(plat));
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sbi_platform_get_features_str(plat, str, sizeof(str));
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sbi_printf("Platform Features : %s\n", str);
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sbi_printf("Platform HART Count : %u\n",
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sbi_platform_hart_count(plat));
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idev = sbi_ipi_get_device();
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sbi_printf("Platform IPI Device : %s\n",
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(idev) ? idev->name : "---");
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tdev = sbi_timer_get_device();
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sbi_printf("Platform Timer Device : %s @ %luHz\n",
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(tdev) ? tdev->name : "---",
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(tdev) ? tdev->timer_freq : 0);
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cdev = sbi_console_get_device();
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sbi_printf("Platform Console Device : %s\n",
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(cdev) ? cdev->name : "---");
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hdev = sbi_hsm_get_device();
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sbi_printf("Platform HSM Device : %s\n",
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(hdev) ? hdev->name : "---");
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pdev = sbi_pmu_get_device();
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sbi_printf("Platform PMU Device : %s\n",
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(pdev) ? pdev->name : "---");
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srdev = sbi_system_reset_get_device(SBI_SRST_RESET_TYPE_COLD_REBOOT, 0);
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sbi_printf("Platform Reboot Device : %s\n",
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(srdev) ? srdev->name : "---");
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srdev = sbi_system_reset_get_device(SBI_SRST_RESET_TYPE_SHUTDOWN, 0);
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sbi_printf("Platform Shutdown Device : %s\n",
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(srdev) ? srdev->name : "---");
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susp_dev = sbi_system_suspend_get_device();
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sbi_printf("Platform Suspend Device : %s\n",
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(susp_dev) ? susp_dev->name : "---");
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cppc_dev = sbi_cppc_get_device();
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sbi_printf("Platform CPPC Device : %s\n",
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(cppc_dev) ? cppc_dev->name : "---");
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/* Firmware details */
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sbi_printf("Firmware Base : 0x%lx\n", scratch->fw_start);
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sbi_printf("Firmware Size : %d KB\n",
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(u32)(scratch->fw_size / 1024));
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sbi_printf("Firmware RW Offset : 0x%lx\n", scratch->fw_rw_offset);
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sbi_printf("Firmware RW Size : %d KB\n",
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(u32)((scratch->fw_size - scratch->fw_rw_offset) / 1024));
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sbi_printf("Firmware Heap Offset : 0x%lx\n", scratch->fw_heap_offset);
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sbi_printf("Firmware Heap Size : "
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"%d KB (total), %d KB (reserved), %d KB (used), %d KB (free)\n",
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(u32)(scratch->fw_heap_size / 1024),
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(u32)(sbi_heap_reserved_space() / 1024),
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(u32)(sbi_heap_used_space() / 1024),
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(u32)(sbi_heap_free_space() / 1024));
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sbi_printf("Firmware Scratch Size : "
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"%d B (total), %d B (used), %d B (free)\n",
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SBI_SCRATCH_SIZE,
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(u32)sbi_scratch_used_space(),
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(u32)(SBI_SCRATCH_SIZE - sbi_scratch_used_space()));
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/* SBI details */
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sbi_printf("Runtime SBI Version : %d.%d\n",
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sbi_ecall_version_major(), sbi_ecall_version_minor());
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sbi_printf("\n");
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}
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static void sbi_boot_print_domains(struct sbi_scratch *scratch)
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{
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if (scratch->options & SBI_SCRATCH_NO_BOOT_PRINTS)
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return;
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/* Domain details */
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sbi_domain_dump_all(" ");
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}
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static void sbi_boot_print_hart(struct sbi_scratch *scratch, u32 hartid)
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{
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int xlen;
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char str[128];
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const struct sbi_domain *dom = sbi_domain_thishart_ptr();
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if (scratch->options & SBI_SCRATCH_NO_BOOT_PRINTS)
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return;
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/* Determine MISA XLEN and MISA string */
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xlen = misa_xlen();
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if (xlen < 1) {
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sbi_printf("Error %d getting MISA XLEN\n", xlen);
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sbi_hart_hang();
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}
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/* Boot HART details */
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sbi_printf("Boot HART ID : %u\n", hartid);
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sbi_printf("Boot HART Domain : %s\n", dom->name);
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sbi_hart_get_priv_version_str(scratch, str, sizeof(str));
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sbi_printf("Boot HART Priv Version : %s\n", str);
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misa_string(xlen, str, sizeof(str));
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sbi_printf("Boot HART Base ISA : %s\n", str);
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sbi_hart_get_extensions_str(scratch, str, sizeof(str));
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sbi_printf("Boot HART ISA Extensions : %s\n", str);
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sbi_printf("Boot HART PMP Count : %d\n",
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sbi_hart_pmp_count(scratch));
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sbi_printf("Boot HART PMP Granularity : %u bits\n",
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sbi_hart_pmp_log2gran(scratch));
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sbi_printf("Boot HART PMP Address Bits: %d\n",
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sbi_hart_pmp_addrbits(scratch));
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sbi_printf("Boot HART MHPM Info : %lu (0x%08x)\n",
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sbi_popcount(sbi_hart_mhpm_mask(scratch)),
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sbi_hart_mhpm_mask(scratch));
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sbi_printf("Boot HART Debug Triggers : %d triggers\n",
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sbi_dbtr_get_total_triggers());
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sbi_hart_delegation_dump(scratch, "Boot HART ", " ");
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}
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static unsigned long coldboot_done;
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static void wait_for_coldboot(struct sbi_scratch *scratch, u32 hartid)
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{
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/* Wait for coldboot to finish */
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while (!__smp_load_acquire(&coldboot_done))
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cpu_relax();
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}
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static void wake_coldboot_harts(struct sbi_scratch *scratch, u32 hartid)
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{
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/* Mark coldboot done */
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__smp_store_release(&coldboot_done, 1);
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}
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static unsigned long entry_count_offset;
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static unsigned long init_count_offset;
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static void __noreturn init_coldboot(struct sbi_scratch *scratch, u32 hartid)
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{
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int rc;
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unsigned long *count;
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const struct sbi_platform *plat = sbi_platform_ptr(scratch);
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/* Note: This has to be first thing in coldboot init sequence */
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rc = sbi_scratch_init(scratch);
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if (rc)
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sbi_hart_hang();
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/* Note: This has to be second thing in coldboot init sequence */
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rc = sbi_heap_init(scratch);
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if (rc)
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sbi_hart_hang();
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/* Note: This has to be the third thing in coldboot init sequence */
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rc = sbi_domain_init(scratch, hartid);
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if (rc)
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sbi_hart_hang();
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entry_count_offset = sbi_scratch_alloc_offset(__SIZEOF_POINTER__);
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if (!entry_count_offset)
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sbi_hart_hang();
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init_count_offset = sbi_scratch_alloc_offset(__SIZEOF_POINTER__);
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if (!init_count_offset)
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sbi_hart_hang();
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count = sbi_scratch_offset_ptr(scratch, entry_count_offset);
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(*count)++;
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rc = sbi_hsm_init(scratch, hartid, true);
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if (rc)
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sbi_hart_hang();
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/*
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* All non-coldboot HARTs do HSM initialization (i.e. enter HSM state
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* machine) at the start of the warmboot path so it is wasteful to
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* have these HARTs busy spin in wait_for_coldboot() until coldboot
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* path is completed.
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*/
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wake_coldboot_harts(scratch, hartid);
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rc = sbi_platform_early_init(plat, true);
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if (rc)
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sbi_hart_hang();
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rc = sbi_hart_init(scratch, true);
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if (rc)
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sbi_hart_hang();
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rc = sbi_console_init(scratch);
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if (rc)
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sbi_hart_hang();
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rc = sbi_sse_init(scratch, true);
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if (rc) {
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sbi_printf("%s: sse init failed (error %d)\n", __func__, rc);
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sbi_hart_hang();
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}
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rc = sbi_pmu_init(scratch, true);
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if (rc) {
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sbi_printf("%s: pmu init failed (error %d)\n",
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__func__, rc);
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sbi_hart_hang();
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}
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rc = sbi_dbtr_init(scratch, true);
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if (rc)
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sbi_hart_hang();
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sbi_boot_print_banner(scratch);
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rc = sbi_irqchip_init(scratch, true);
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if (rc) {
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sbi_printf("%s: irqchip init failed (error %d)\n",
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__func__, rc);
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sbi_hart_hang();
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}
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rc = sbi_ipi_init(scratch, true);
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if (rc) {
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sbi_printf("%s: ipi init failed (error %d)\n", __func__, rc);
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sbi_hart_hang();
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}
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rc = sbi_tlb_init(scratch, true);
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if (rc) {
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sbi_printf("%s: tlb init failed (error %d)\n", __func__, rc);
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sbi_hart_hang();
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}
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rc = sbi_timer_init(scratch, true);
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if (rc) {
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sbi_printf("%s: timer init failed (error %d)\n", __func__, rc);
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sbi_hart_hang();
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}
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/*
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* Note: Finalize domains after HSM initialization so that we
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* can startup non-root domains.
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* Note: Finalize domains before HART PMP configuration so
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* that we use correct domain for configuring PMP.
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*/
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rc = sbi_domain_finalize(scratch, hartid);
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if (rc) {
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sbi_printf("%s: domain finalize failed (error %d)\n",
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__func__, rc);
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sbi_hart_hang();
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}
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/*
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* Note: Platform final initialization should be after finalizing
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* domains so that it sees correct domain assignment and PMP
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* configuration for FDT fixups.
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*/
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rc = sbi_platform_final_init(plat, true);
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if (rc) {
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sbi_printf("%s: platform final init failed (error %d)\n",
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__func__, rc);
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sbi_hart_hang();
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}
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/*
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* Note: Ecall initialization should be after platform final
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* initialization so that all available platform devices are
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* already registered.
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*/
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rc = sbi_ecall_init();
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if (rc) {
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sbi_printf("%s: ecall init failed (error %d)\n", __func__, rc);
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sbi_hart_hang();
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}
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sbi_boot_print_general(scratch);
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sbi_boot_print_domains(scratch);
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sbi_boot_print_hart(scratch, hartid);
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run_all_tests();
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/*
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* Configure PMP at last because if SMEPMP is detected,
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* M-mode access to the S/U space will be rescinded.
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*/
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rc = sbi_hart_pmp_configure(scratch);
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if (rc) {
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sbi_printf("%s: PMP configure failed (error %d)\n",
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__func__, rc);
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sbi_hart_hang();
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}
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count = sbi_scratch_offset_ptr(scratch, init_count_offset);
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(*count)++;
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sbi_hsm_hart_start_finish(scratch, hartid);
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}
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static void __noreturn init_warm_startup(struct sbi_scratch *scratch,
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u32 hartid)
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{
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int rc;
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unsigned long *count;
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const struct sbi_platform *plat = sbi_platform_ptr(scratch);
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if (!entry_count_offset || !init_count_offset)
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sbi_hart_hang();
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count = sbi_scratch_offset_ptr(scratch, entry_count_offset);
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(*count)++;
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/* Note: This has to be first thing in warmboot init sequence */
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rc = sbi_hsm_init(scratch, hartid, false);
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if (rc)
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sbi_hart_hang();
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rc = sbi_platform_early_init(plat, false);
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if (rc)
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sbi_hart_hang();
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rc = sbi_hart_init(scratch, false);
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if (rc)
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sbi_hart_hang();
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rc = sbi_sse_init(scratch, false);
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if (rc)
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sbi_hart_hang();
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rc = sbi_pmu_init(scratch, false);
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if (rc)
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sbi_hart_hang();
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rc = sbi_dbtr_init(scratch, false);
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if (rc)
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sbi_hart_hang();
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rc = sbi_irqchip_init(scratch, false);
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if (rc)
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sbi_hart_hang();
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rc = sbi_ipi_init(scratch, false);
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if (rc)
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sbi_hart_hang();
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rc = sbi_tlb_init(scratch, false);
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if (rc)
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sbi_hart_hang();
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rc = sbi_timer_init(scratch, false);
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if (rc)
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sbi_hart_hang();
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rc = sbi_platform_final_init(plat, false);
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if (rc)
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sbi_hart_hang();
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/*
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* Configure PMP at last because if SMEPMP is detected,
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* M-mode access to the S/U space will be rescinded.
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*/
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rc = sbi_hart_pmp_configure(scratch);
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if (rc)
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sbi_hart_hang();
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count = sbi_scratch_offset_ptr(scratch, init_count_offset);
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(*count)++;
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sbi_hsm_hart_start_finish(scratch, hartid);
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}
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static void __noreturn init_warm_resume(struct sbi_scratch *scratch,
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u32 hartid)
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{
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int rc;
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sbi_hsm_hart_resume_start(scratch);
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rc = sbi_hart_reinit(scratch);
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if (rc)
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sbi_hart_hang();
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rc = sbi_hart_pmp_configure(scratch);
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if (rc)
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sbi_hart_hang();
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sbi_hsm_hart_resume_finish(scratch, hartid);
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}
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static void __noreturn init_warmboot(struct sbi_scratch *scratch, u32 hartid)
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{
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int hstate;
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|
|
wait_for_coldboot(scratch, hartid);
|
|
|
|
hstate = sbi_hsm_hart_get_state(sbi_domain_thishart_ptr(), hartid);
|
|
if (hstate < 0)
|
|
sbi_hart_hang();
|
|
|
|
if (hstate == SBI_HSM_STATE_SUSPENDED) {
|
|
init_warm_resume(scratch, hartid);
|
|
} else {
|
|
sbi_ipi_raw_clear(sbi_hartid_to_hartindex(hartid));
|
|
init_warm_startup(scratch, hartid);
|
|
}
|
|
}
|
|
|
|
static atomic_t coldboot_lottery = ATOMIC_INITIALIZER(0);
|
|
|
|
/**
|
|
* Initialize OpenSBI library for current HART and jump to next
|
|
* booting stage.
|
|
*
|
|
* The function expects following:
|
|
* 1. The 'mscratch' CSR is pointing to sbi_scratch of current HART
|
|
* 2. Stack pointer (SP) is setup for current HART
|
|
* 3. Interrupts are disabled in MSTATUS CSR
|
|
* 4. All interrupts are disabled in MIE CSR
|
|
*
|
|
* @param scratch pointer to sbi_scratch of current HART
|
|
*/
|
|
void __noreturn sbi_init(struct sbi_scratch *scratch)
|
|
{
|
|
u32 i, h;
|
|
bool hartid_valid = false;
|
|
bool next_mode_supported = false;
|
|
bool coldboot = false;
|
|
u32 hartid = current_hartid();
|
|
const struct sbi_platform *plat = sbi_platform_ptr(scratch);
|
|
|
|
for (i = 0; i < plat->hart_count; i++) {
|
|
h = (plat->hart_index2id) ? plat->hart_index2id[i] : i;
|
|
if (h == hartid)
|
|
hartid_valid = true;
|
|
}
|
|
if (!hartid_valid)
|
|
sbi_hart_hang();
|
|
|
|
switch (scratch->next_mode) {
|
|
case PRV_M:
|
|
next_mode_supported = true;
|
|
break;
|
|
case PRV_S:
|
|
if (misa_extension('S'))
|
|
next_mode_supported = true;
|
|
break;
|
|
case PRV_U:
|
|
if (misa_extension('U'))
|
|
next_mode_supported = true;
|
|
break;
|
|
default:
|
|
sbi_hart_hang();
|
|
}
|
|
|
|
/*
|
|
* Only the HART supporting privilege mode specified in the
|
|
* scratch->next_mode should be allowed to become the coldboot
|
|
* HART because the coldboot HART will be directly jumping to
|
|
* the next booting stage.
|
|
*
|
|
* We use a lottery mechanism to select coldboot HART among
|
|
* HARTs which satisfy above condition.
|
|
*/
|
|
|
|
if (sbi_platform_cold_boot_allowed(plat, hartid)) {
|
|
if (next_mode_supported &&
|
|
atomic_xchg(&coldboot_lottery, 1) == 0)
|
|
coldboot = true;
|
|
}
|
|
|
|
/*
|
|
* Do platform specific nascent (very early) initialization so
|
|
* that platform can initialize platform specific per-HART CSRs
|
|
* or per-HART devices.
|
|
*/
|
|
if (sbi_platform_nascent_init(plat))
|
|
sbi_hart_hang();
|
|
|
|
if (coldboot)
|
|
init_coldboot(scratch, hartid);
|
|
else
|
|
init_warmboot(scratch, hartid);
|
|
}
|
|
|
|
unsigned long sbi_entry_count(u32 hartid)
|
|
{
|
|
struct sbi_scratch *scratch;
|
|
unsigned long *entry_count;
|
|
|
|
if (!entry_count_offset)
|
|
return 0;
|
|
|
|
scratch = sbi_hartid_to_scratch(hartid);
|
|
if (!scratch)
|
|
return 0;
|
|
|
|
entry_count = sbi_scratch_offset_ptr(scratch, entry_count_offset);
|
|
|
|
return *entry_count;
|
|
}
|
|
|
|
unsigned long sbi_init_count(u32 hartid)
|
|
{
|
|
struct sbi_scratch *scratch;
|
|
unsigned long *init_count;
|
|
|
|
if (!init_count_offset)
|
|
return 0;
|
|
|
|
scratch = sbi_hartid_to_scratch(hartid);
|
|
if (!scratch)
|
|
return 0;
|
|
|
|
init_count = sbi_scratch_offset_ptr(scratch, init_count_offset);
|
|
|
|
return *init_count;
|
|
}
|
|
|
|
/**
|
|
* Exit OpenSBI library for current HART and stop HART
|
|
*
|
|
* The function expects following:
|
|
* 1. The 'mscratch' CSR is pointing to sbi_scratch of current HART
|
|
* 2. Stack pointer (SP) is setup for current HART
|
|
*
|
|
* @param scratch pointer to sbi_scratch of current HART
|
|
*/
|
|
void __noreturn sbi_exit(struct sbi_scratch *scratch)
|
|
{
|
|
u32 hartid = current_hartid();
|
|
const struct sbi_platform *plat = sbi_platform_ptr(scratch);
|
|
|
|
if (!sbi_hartid_valid(hartid))
|
|
sbi_hart_hang();
|
|
|
|
sbi_platform_early_exit(plat);
|
|
|
|
sbi_sse_exit(scratch);
|
|
|
|
sbi_pmu_exit(scratch);
|
|
|
|
sbi_timer_exit(scratch);
|
|
|
|
sbi_ipi_exit(scratch);
|
|
|
|
sbi_irqchip_exit(scratch);
|
|
|
|
sbi_platform_final_exit(plat);
|
|
|
|
sbi_hsm_exit(scratch);
|
|
}
|