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arm: zynq: Add lowlevel initialization to C
Do lowlevel initialization directly in C. Zynq do not require to do it in asm. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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59c651f4e2
commit
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2 changed files with 70 additions and 2 deletions
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@ -21,9 +21,33 @@
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* MA 02111-1307 USA
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* MA 02111-1307 USA
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*/
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*/
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#include <common.h>
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/hardware.h>
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inline void lowlevel_init(void) {}
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void lowlevel_init(void)
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{
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zynq_slcr_unlock();
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/* remap DDR to zero, FILTERSTART */
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writel(0, &scu_base->filter_start);
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/* Device config APB, unlock the PCAP */
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writel(0x757BDF0D, &devcfg_base->unlock);
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writel(0xFFFFFFFF, &devcfg_base->rom_shadow);
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/* OCM_CFG, Mask out the ROM, map ram into upper addresses */
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writel(0x1F, &slcr_base->ocm_cfg);
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/* FPGA_RST_CTRL, clear resets on AXI fabric ports */
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writel(0x0, &slcr_base->fpga_rst_ctrl);
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/* TZ_DDR_RAM, Set DDR trust zone non-secure */
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writel(0xFFFFFFFF, &slcr_base->trust_zone);
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/* Set urgent bits with register */
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writel(0x0, &slcr_base->ddr_urgent_sel);
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/* Urgent write, ports S2/S3 */
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writel(0xC, &slcr_base->ddr_urgent);
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zynq_slcr_lock();
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}
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void reset_cpu(ulong addr)
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void reset_cpu(ulong addr)
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{
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{
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@ -24,6 +24,8 @@
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#define _ASM_ARCH_HARDWARE_H
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#define _ASM_ARCH_HARDWARE_H
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#define XPSS_SYS_CTRL_BASEADDR 0xF8000000
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#define XPSS_SYS_CTRL_BASEADDR 0xF8000000
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#define XPSS_DEV_CFG_APB_BASEADDR 0xF8007000
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#define XPSS_SCU_BASEADDR 0xF8F00000
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/* Reflect slcr offsets */
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/* Reflect slcr offsets */
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struct slcr_regs {
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struct slcr_regs {
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@ -32,10 +34,52 @@ struct slcr_regs {
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u32 slcr_unlock; /* 0x8 */
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u32 slcr_unlock; /* 0x8 */
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u32 reserved1[125];
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u32 reserved1[125];
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u32 pss_rst_ctrl; /* 0x200 */
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u32 pss_rst_ctrl; /* 0x200 */
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u32 reserved2[21];
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u32 reserved2[15];
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u32 fpga_rst_ctrl; /* 0x240 */
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u32 reserved3[5];
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u32 reboot_status; /* 0x258 */
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u32 reboot_status; /* 0x258 */
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u32 boot_mode; /* 0x25c */
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u32 reserved4[116];
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u32 trust_zone; /* 0x430 */ /* FIXME */
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u32 reserved5[115];
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u32 ddr_urgent; /* 0x600 */
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u32 reserved6[6];
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u32 ddr_urgent_sel; /* 0x61c */
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u32 reserved7[188];
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u32 ocm_cfg; /* 0x910 */
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};
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};
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#define slcr_base ((struct slcr_regs *) XPSS_SYS_CTRL_BASEADDR)
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#define slcr_base ((struct slcr_regs *) XPSS_SYS_CTRL_BASEADDR)
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struct devcfg_regs {
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u32 ctrl; /* 0x0 */
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u32 lock; /* 0x4 */
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u32 cfg; /* 0x8 */
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u32 int_sts; /* 0xc */
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u32 int_mask; /* 0x10 */
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u32 status; /* 0x14 */
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u32 dma_src_addr; /* 0x18 */
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u32 dma_dst_addr; /* 0x1c */
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u32 dma_src_len; /* 0x20 */
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u32 dma_dst_len; /* 0x24 */
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u32 rom_shadow; /* 0x28 */
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u32 reserved1[2];
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u32 unlock; /* 0x34 */
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u32 reserved2[18];
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u32 mctrl; /* 0x80 */
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u32 reserved3;
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u32 write_count; /* 0x88 */
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u32 read_count; /* 0x8c */
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};
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#define devcfg_base ((struct devcfg_regs *) XPSS_DEV_CFG_APB_BASEADDR)
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struct scu_regs {
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u32 reserved1[16];
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u32 filter_start; /* 0x40 */
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u32 filter_end; /* 0x44 */
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};
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#define scu_base ((struct scu_regs *) XPSS_SCU_BASEADDR)
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#endif /* _ASM_ARCH_HARDWARE_H */
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#endif /* _ASM_ARCH_HARDWARE_H */
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