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tegra: video: Support serial output resource (SOR) on tegra124
The SOR is required for talking to eDP LCD panels. Add a driver for this which will be used by the DisplayPort driver. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Anatolij Gustschin <agust@denx.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
This commit is contained in:
Simon Glass
Tom Warren
parent
ec44671b35
commit
00f3732752
6 changed files with 1815 additions and 0 deletions
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@ -52,3 +52,5 @@ obj-$(CONFIG_FORMIKE) += formike.o
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obj-$(CONFIG_LG4573) += lg4573.o
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obj-$(CONFIG_AM335X_LCD) += am335x-fb.o
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obj-$(CONFIG_VIDEO_PARADE) += parade.o
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obj-${CONFIG_VIDEO_TEGRA124} += tegra124/
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7
drivers/video/tegra124/Makefile
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7
drivers/video/tegra124/Makefile
Normal file
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@ -0,0 +1,7 @@
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#
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# Copyright (c) 2014 Google, Inc
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y += sor.o
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896
drivers/video/tegra124/sor.c
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896
drivers/video/tegra124/sor.c
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@ -0,0 +1,896 @@
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/*
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* Copyright (c) 2011-2013, NVIDIA Corporation.
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#include <common.h>
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#include <errno.h>
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#include <fdtdec.h>
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#include <malloc.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch-tegra/dc.h>
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#include "displayport.h"
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#include "sor.h"
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DECLARE_GLOBAL_DATA_PTR;
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#define DEBUG_SOR 0
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#define APBDEV_PMC_DPD_SAMPLE 0x20
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#define APBDEV_PMC_DPD_SAMPLE_ON_DISABLE 0
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#define APBDEV_PMC_DPD_SAMPLE_ON_ENABLE 1
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#define APBDEV_PMC_SEL_DPD_TIM 0x1c8
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#define APBDEV_PMC_SEL_DPD_TIM_SEL_DPD_TIM_DEFAULT 0x7f
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#define APBDEV_PMC_IO_DPD2_REQ 0x1c0
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#define APBDEV_PMC_IO_DPD2_REQ_LVDS_SHIFT 25
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#define APBDEV_PMC_IO_DPD2_REQ_LVDS_OFF (0 << 25)
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#define APBDEV_PMC_IO_DPD2_REQ_LVDS_ON (1 << 25)
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#define APBDEV_PMC_IO_DPD2_REQ_CODE_SHIFT 30
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#define APBDEV_PMC_IO_DPD2_REQ_CODE_DEFAULT_MASK (0x3 << 30)
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#define APBDEV_PMC_IO_DPD2_REQ_CODE_IDLE (0 << 30)
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#define APBDEV_PMC_IO_DPD2_REQ_CODE_DPD_OFF (1 << 30)
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#define APBDEV_PMC_IO_DPD2_REQ_CODE_DPD_ON (2 << 30)
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#define APBDEV_PMC_IO_DPD2_STATUS 0x1c4
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#define APBDEV_PMC_IO_DPD2_STATUS_LVDS_SHIFT 25
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#define APBDEV_PMC_IO_DPD2_STATUS_LVDS_OFF (0 << 25)
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#define APBDEV_PMC_IO_DPD2_STATUS_LVDS_ON (1 << 25)
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static inline u32 tegra_sor_readl(struct tegra_dc_sor_data *sor, u32 reg)
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{
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return readl((u32 *)sor->base + reg);
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}
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static inline void tegra_sor_writel(struct tegra_dc_sor_data *sor, u32 reg,
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u32 val)
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{
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writel(val, (u32 *)sor->base + reg);
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}
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static inline void tegra_sor_write_field(struct tegra_dc_sor_data *sor,
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u32 reg, u32 mask, u32 val)
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{
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u32 reg_val = tegra_sor_readl(sor, reg);
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reg_val &= ~mask;
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reg_val |= val;
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tegra_sor_writel(sor, reg, reg_val);
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}
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static int tegra_dc_sor_poll_register(struct tegra_dc_sor_data *sor, u32 reg,
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u32 mask, u32 exp_val,
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int poll_interval_us, int timeout_ms)
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{
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u32 reg_val = 0;
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ulong start;
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start = get_timer(0);
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do {
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reg_val = tegra_sor_readl(sor, reg);
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if (((reg_val & mask) == exp_val))
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return 0;
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udelay(poll_interval_us);
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} while (get_timer(start) < timeout_ms);
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debug("sor_poll_register 0x%x: timeout, (reg_val)0x%08x & (mask)0x%08x != (exp_val)0x%08x\n",
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reg, reg_val, mask, exp_val);
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return -ETIMEDOUT;
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}
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int tegra_dc_sor_set_power_state(struct tegra_dc_sor_data *sor, int pu_pd)
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{
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u32 reg_val;
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u32 orig_val;
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orig_val = tegra_sor_readl(sor, PWR);
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reg_val = pu_pd ? PWR_NORMAL_STATE_PU :
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PWR_NORMAL_STATE_PD; /* normal state only */
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if (reg_val == orig_val)
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return 0; /* No update needed */
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reg_val |= PWR_SETTING_NEW_TRIGGER;
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tegra_sor_writel(sor, PWR, reg_val);
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/* Poll to confirm it is done */
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if (tegra_dc_sor_poll_register(sor, PWR,
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PWR_SETTING_NEW_DEFAULT_MASK,
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PWR_SETTING_NEW_DONE,
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100, TEGRA_SOR_TIMEOUT_MS)) {
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debug("dc timeout waiting for SOR_PWR = NEW_DONE\n");
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return -EFAULT;
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}
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return 0;
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}
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void tegra_dc_sor_set_dp_linkctl(struct tegra_dc_sor_data *sor, int ena,
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u8 training_pattern,
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const struct tegra_dp_link_config *link_cfg)
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{
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u32 reg_val;
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reg_val = tegra_sor_readl(sor, DP_LINKCTL(sor->portnum));
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if (ena)
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reg_val |= DP_LINKCTL_ENABLE_YES;
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else
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reg_val &= DP_LINKCTL_ENABLE_NO;
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reg_val &= ~DP_LINKCTL_TUSIZE_MASK;
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reg_val |= (link_cfg->tu_size << DP_LINKCTL_TUSIZE_SHIFT);
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if (link_cfg->enhanced_framing)
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reg_val |= DP_LINKCTL_ENHANCEDFRAME_ENABLE;
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tegra_sor_writel(sor, DP_LINKCTL(sor->portnum), reg_val);
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switch (training_pattern) {
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case training_pattern_1:
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tegra_sor_writel(sor, DP_TPG, 0x41414141);
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break;
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case training_pattern_2:
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case training_pattern_3:
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reg_val = (link_cfg->link_bw == SOR_LINK_SPEED_G5_4) ?
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0x43434343 : 0x42424242;
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tegra_sor_writel(sor, DP_TPG, reg_val);
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break;
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default:
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tegra_sor_writel(sor, DP_TPG, 0x50505050);
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break;
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}
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}
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static int tegra_dc_sor_enable_lane_sequencer(struct tegra_dc_sor_data *sor,
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int pu, int is_lvds)
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{
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u32 reg_val;
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/* SOR lane sequencer */
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if (pu) {
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reg_val = LANE_SEQ_CTL_SETTING_NEW_TRIGGER |
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LANE_SEQ_CTL_SEQUENCE_DOWN |
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LANE_SEQ_CTL_NEW_POWER_STATE_PU;
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} else {
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reg_val = LANE_SEQ_CTL_SETTING_NEW_TRIGGER |
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LANE_SEQ_CTL_SEQUENCE_UP |
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LANE_SEQ_CTL_NEW_POWER_STATE_PD;
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}
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if (is_lvds)
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reg_val |= 15 << LANE_SEQ_CTL_DELAY_SHIFT;
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else
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reg_val |= 1 << LANE_SEQ_CTL_DELAY_SHIFT;
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tegra_sor_writel(sor, LANE_SEQ_CTL, reg_val);
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if (tegra_dc_sor_poll_register(sor, LANE_SEQ_CTL,
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LANE_SEQ_CTL_SETTING_MASK,
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LANE_SEQ_CTL_SETTING_NEW_DONE,
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100, TEGRA_SOR_TIMEOUT_MS)) {
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debug("dp: timeout while waiting for SOR lane sequencer to power down lanes\n");
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return -1;
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}
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return 0;
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}
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static int tegra_dc_sor_power_dplanes(struct tegra_dc_sor_data *sor,
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u32 lane_count, int pu)
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{
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u32 reg_val;
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reg_val = tegra_sor_readl(sor, DP_PADCTL(sor->portnum));
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if (pu) {
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switch (lane_count) {
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case 4:
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reg_val |= (DP_PADCTL_PD_TXD_3_NO |
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DP_PADCTL_PD_TXD_2_NO);
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/* fall through */
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case 2:
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reg_val |= DP_PADCTL_PD_TXD_1_NO;
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case 1:
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reg_val |= DP_PADCTL_PD_TXD_0_NO;
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break;
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default:
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debug("dp: invalid lane number %d\n", lane_count);
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return -1;
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}
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tegra_sor_writel(sor, DP_PADCTL(sor->portnum), reg_val);
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tegra_dc_sor_set_lane_count(sor, lane_count);
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}
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return tegra_dc_sor_enable_lane_sequencer(sor, pu, 0);
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}
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void tegra_dc_sor_set_panel_power(struct tegra_dc_sor_data *sor,
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int power_up)
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{
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u32 reg_val;
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reg_val = tegra_sor_readl(sor, DP_PADCTL(sor->portnum));
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if (power_up)
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reg_val |= DP_PADCTL_PAD_CAL_PD_POWERUP;
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else
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reg_val &= ~DP_PADCTL_PAD_CAL_PD_POWERUP;
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tegra_sor_writel(sor, DP_PADCTL(sor->portnum), reg_val);
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}
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static void tegra_dc_sor_config_pwm(struct tegra_dc_sor_data *sor, u32 pwm_div,
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u32 pwm_dutycycle)
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{
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tegra_sor_writel(sor, PWM_DIV, pwm_div);
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tegra_sor_writel(sor, PWM_CTL,
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(pwm_dutycycle & PWM_CTL_DUTY_CYCLE_MASK) |
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PWM_CTL_SETTING_NEW_TRIGGER);
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if (tegra_dc_sor_poll_register(sor, PWM_CTL,
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PWM_CTL_SETTING_NEW_SHIFT,
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PWM_CTL_SETTING_NEW_DONE,
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100, TEGRA_SOR_TIMEOUT_MS)) {
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debug("dp: timeout while waiting for SOR PWM setting\n");
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}
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}
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static void tegra_dc_sor_set_dp_mode(struct tegra_dc_sor_data *sor,
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const struct tegra_dp_link_config *link_cfg)
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{
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u32 reg_val;
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tegra_dc_sor_set_link_bandwidth(sor, link_cfg->link_bw);
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tegra_dc_sor_set_dp_linkctl(sor, 1, training_pattern_none, link_cfg);
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reg_val = tegra_sor_readl(sor, DP_CONFIG(sor->portnum));
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reg_val &= ~DP_CONFIG_WATERMARK_MASK;
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reg_val |= link_cfg->watermark;
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reg_val &= ~DP_CONFIG_ACTIVESYM_COUNT_MASK;
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reg_val |= (link_cfg->active_count <<
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DP_CONFIG_ACTIVESYM_COUNT_SHIFT);
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reg_val &= ~DP_CONFIG_ACTIVESYM_FRAC_MASK;
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reg_val |= (link_cfg->active_frac <<
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DP_CONFIG_ACTIVESYM_FRAC_SHIFT);
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if (link_cfg->activepolarity)
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reg_val |= DP_CONFIG_ACTIVESYM_POLARITY_POSITIVE;
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else
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reg_val &= ~DP_CONFIG_ACTIVESYM_POLARITY_POSITIVE;
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reg_val |= (DP_CONFIG_ACTIVESYM_CNTL_ENABLE |
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DP_CONFIG_RD_RESET_VAL_NEGATIVE);
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tegra_sor_writel(sor, DP_CONFIG(sor->portnum), reg_val);
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/* program h/vblank sym */
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tegra_sor_write_field(sor, DP_AUDIO_HBLANK_SYMBOLS,
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DP_AUDIO_HBLANK_SYMBOLS_MASK,
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link_cfg->hblank_sym);
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tegra_sor_write_field(sor, DP_AUDIO_VBLANK_SYMBOLS,
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DP_AUDIO_VBLANK_SYMBOLS_MASK,
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link_cfg->vblank_sym);
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}
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static inline void tegra_dc_sor_super_update(struct tegra_dc_sor_data *sor)
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{
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tegra_sor_writel(sor, SUPER_STATE0, 0);
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tegra_sor_writel(sor, SUPER_STATE0, 1);
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tegra_sor_writel(sor, SUPER_STATE0, 0);
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}
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static inline void tegra_dc_sor_update(struct tegra_dc_sor_data *sor)
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{
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tegra_sor_writel(sor, STATE0, 0);
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tegra_sor_writel(sor, STATE0, 1);
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tegra_sor_writel(sor, STATE0, 0);
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}
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static int tegra_dc_sor_io_set_dpd(struct tegra_dc_sor_data *sor, int up)
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{
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u32 reg_val;
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void *pmc_base = sor->pmc_base;
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if (up) {
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writel(APBDEV_PMC_DPD_SAMPLE_ON_ENABLE,
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pmc_base + APBDEV_PMC_DPD_SAMPLE);
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writel(10, pmc_base + APBDEV_PMC_SEL_DPD_TIM);
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}
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reg_val = readl(pmc_base + APBDEV_PMC_IO_DPD2_REQ);
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reg_val &= ~(APBDEV_PMC_IO_DPD2_REQ_LVDS_ON ||
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APBDEV_PMC_IO_DPD2_REQ_CODE_DEFAULT_MASK);
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reg_val = up ? APBDEV_PMC_IO_DPD2_REQ_LVDS_ON |
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APBDEV_PMC_IO_DPD2_REQ_CODE_DPD_OFF :
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APBDEV_PMC_IO_DPD2_REQ_LVDS_OFF |
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APBDEV_PMC_IO_DPD2_REQ_CODE_DPD_ON;
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writel(reg_val, pmc_base + APBDEV_PMC_IO_DPD2_REQ);
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/* Polling */
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u32 temp = 10 * 1000;
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do {
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udelay(20);
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reg_val = readl(pmc_base + APBDEV_PMC_IO_DPD2_STATUS);
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if (temp > 20)
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temp -= 20;
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else
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break;
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} while ((reg_val & APBDEV_PMC_IO_DPD2_STATUS_LVDS_ON) != 0);
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if ((reg_val & APBDEV_PMC_IO_DPD2_STATUS_LVDS_ON) != 0) {
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debug("PMC_IO_DPD2 polling failed (0x%x)\n", reg_val);
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return -EIO;
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}
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if (up) {
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writel(APBDEV_PMC_DPD_SAMPLE_ON_DISABLE,
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pmc_base + APBDEV_PMC_DPD_SAMPLE);
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}
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return 0;
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}
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void tegra_dc_sor_set_internal_panel(struct tegra_dc_sor_data *sor, int is_int)
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{
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u32 reg_val;
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reg_val = tegra_sor_readl(sor, DP_SPARE(sor->portnum));
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if (is_int)
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reg_val |= DP_SPARE_PANEL_INTERNAL;
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else
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reg_val &= ~DP_SPARE_PANEL_INTERNAL;
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reg_val |= DP_SPARE_SOR_CLK_SEL_MACRO_SORCLK |
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DP_SPARE_SEQ_ENABLE_YES;
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tegra_sor_writel(sor, DP_SPARE(sor->portnum), reg_val);
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}
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void tegra_dc_sor_read_link_config(struct tegra_dc_sor_data *sor, u8 *link_bw,
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u8 *lane_count)
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{
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u32 reg_val;
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reg_val = tegra_sor_readl(sor, CLK_CNTRL);
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*link_bw = (reg_val & CLK_CNTRL_DP_LINK_SPEED_MASK)
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>> CLK_CNTRL_DP_LINK_SPEED_SHIFT;
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reg_val = tegra_sor_readl(sor,
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DP_LINKCTL(sor->portnum));
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switch (reg_val & DP_LINKCTL_LANECOUNT_MASK) {
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case DP_LINKCTL_LANECOUNT_ZERO:
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*lane_count = 0;
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break;
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case DP_LINKCTL_LANECOUNT_ONE:
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*lane_count = 1;
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break;
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case DP_LINKCTL_LANECOUNT_TWO:
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*lane_count = 2;
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break;
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case DP_LINKCTL_LANECOUNT_FOUR:
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*lane_count = 4;
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break;
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default:
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printf("Unknown lane count\n");
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}
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}
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void tegra_dc_sor_set_link_bandwidth(struct tegra_dc_sor_data *sor, u8 link_bw)
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{
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tegra_sor_write_field(sor, CLK_CNTRL,
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CLK_CNTRL_DP_LINK_SPEED_MASK,
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link_bw << CLK_CNTRL_DP_LINK_SPEED_SHIFT);
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}
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void tegra_dc_sor_set_lane_count(struct tegra_dc_sor_data *sor, u8 lane_count)
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{
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u32 reg_val;
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reg_val = tegra_sor_readl(sor, DP_LINKCTL(sor->portnum));
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reg_val &= ~DP_LINKCTL_LANECOUNT_MASK;
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switch (lane_count) {
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case 0:
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break;
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case 1:
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reg_val |= DP_LINKCTL_LANECOUNT_ONE;
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break;
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case 2:
|
||||
reg_val |= DP_LINKCTL_LANECOUNT_TWO;
|
||||
break;
|
||||
case 4:
|
||||
reg_val |= DP_LINKCTL_LANECOUNT_FOUR;
|
||||
break;
|
||||
default:
|
||||
/* 0 should be handled earlier. */
|
||||
printf("dp: Invalid lane count %d\n", lane_count);
|
||||
return;
|
||||
}
|
||||
tegra_sor_writel(sor, DP_LINKCTL(sor->portnum), reg_val);
|
||||
}
|
||||
|
||||
/*
|
||||
* The SOR power sequencer does not work for t124 so SW has to
|
||||
* go through the power sequence manually
|
||||
* Power up steps from spec:
|
||||
* STEP PDPORT PDPLL PDBG PLLVCOD PLLCAPD E_DPD PDCAL
|
||||
* 1 1 1 1 1 1 1 1
|
||||
* 2 1 1 1 1 1 0 1
|
||||
* 3 1 1 0 1 1 0 1
|
||||
* 4 1 0 0 0 0 0 1
|
||||
* 5 0 0 0 0 0 0 1
|
||||
*/
|
||||
static int tegra_dc_sor_power_up(struct tegra_dc_sor_data *sor, int is_lvds)
|
||||
{
|
||||
int ret;
|
||||
|
||||
if (sor->power_is_up)
|
||||
return 0;
|
||||
|
||||
/* Set link bw */
|
||||
tegra_dc_sor_set_link_bandwidth(sor, is_lvds ?
|
||||
CLK_CNTRL_DP_LINK_SPEED_LVDS :
|
||||
CLK_CNTRL_DP_LINK_SPEED_G1_62);
|
||||
|
||||
/* step 1 */
|
||||
tegra_sor_write_field(sor, PLL2,
|
||||
PLL2_AUX7_PORT_POWERDOWN_MASK | /* PDPORT */
|
||||
PLL2_AUX6_BANDGAP_POWERDOWN_MASK | /* PDBG */
|
||||
PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_MASK, /* PLLCAPD */
|
||||
PLL2_AUX7_PORT_POWERDOWN_ENABLE |
|
||||
PLL2_AUX6_BANDGAP_POWERDOWN_ENABLE |
|
||||
PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_ENABLE);
|
||||
tegra_sor_write_field(sor, PLL0, PLL0_PWR_MASK | /* PDPLL */
|
||||
PLL0_VCOPD_MASK, /* PLLVCOPD */
|
||||
PLL0_PWR_OFF | PLL0_VCOPD_ASSERT);
|
||||
tegra_sor_write_field(sor, DP_PADCTL(sor->portnum),
|
||||
DP_PADCTL_PAD_CAL_PD_POWERDOWN, /* PDCAL */
|
||||
DP_PADCTL_PAD_CAL_PD_POWERDOWN);
|
||||
|
||||
/* step 2 */
|
||||
ret = tegra_dc_sor_io_set_dpd(sor, 1);
|
||||
if (ret)
|
||||
return ret;
|
||||
udelay(15);
|
||||
|
||||
/* step 3 */
|
||||
tegra_sor_write_field(sor, PLL2,
|
||||
PLL2_AUX6_BANDGAP_POWERDOWN_MASK,
|
||||
PLL2_AUX6_BANDGAP_POWERDOWN_DISABLE);
|
||||
udelay(25);
|
||||
|
||||
/* step 4 */
|
||||
tegra_sor_write_field(sor, PLL0,
|
||||
PLL0_PWR_MASK | /* PDPLL */
|
||||
PLL0_VCOPD_MASK, /* PLLVCOPD */
|
||||
PLL0_PWR_ON | PLL0_VCOPD_RESCIND);
|
||||
/* PLLCAPD */
|
||||
tegra_sor_write_field(sor, PLL2,
|
||||
PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_MASK,
|
||||
PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_DISABLE);
|
||||
udelay(225);
|
||||
|
||||
/* step 5 PDPORT */
|
||||
tegra_sor_write_field(sor, PLL2,
|
||||
PLL2_AUX7_PORT_POWERDOWN_MASK,
|
||||
PLL2_AUX7_PORT_POWERDOWN_DISABLE);
|
||||
|
||||
sor->power_is_up = 1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if DEBUG_SOR
|
||||
static void dump_sor_reg(struct tegra_dc_sor_data *sor)
|
||||
{
|
||||
#define DUMP_REG(a) printk(BIOS_INFO, "%-32s %03x %08x\n", \
|
||||
#a, a, tegra_sor_readl(sor, a));
|
||||
|
||||
DUMP_REG(SUPER_STATE0);
|
||||
DUMP_REG(SUPER_STATE1);
|
||||
DUMP_REG(STATE0);
|
||||
DUMP_REG(STATE1);
|
||||
DUMP_REG(NV_HEAD_STATE0(0));
|
||||
DUMP_REG(NV_HEAD_STATE0(1));
|
||||
DUMP_REG(NV_HEAD_STATE1(0));
|
||||
DUMP_REG(NV_HEAD_STATE1(1));
|
||||
DUMP_REG(NV_HEAD_STATE2(0));
|
||||
DUMP_REG(NV_HEAD_STATE2(1));
|
||||
DUMP_REG(NV_HEAD_STATE3(0));
|
||||
DUMP_REG(NV_HEAD_STATE3(1));
|
||||
DUMP_REG(NV_HEAD_STATE4(0));
|
||||
DUMP_REG(NV_HEAD_STATE4(1));
|
||||
DUMP_REG(NV_HEAD_STATE5(0));
|
||||
DUMP_REG(NV_HEAD_STATE5(1));
|
||||
DUMP_REG(CRC_CNTRL);
|
||||
DUMP_REG(CLK_CNTRL);
|
||||
DUMP_REG(CAP);
|
||||
DUMP_REG(PWR);
|
||||
DUMP_REG(TEST);
|
||||
DUMP_REG(PLL0);
|
||||
DUMP_REG(PLL1);
|
||||
DUMP_REG(PLL2);
|
||||
DUMP_REG(PLL3);
|
||||
DUMP_REG(CSTM);
|
||||
DUMP_REG(LVDS);
|
||||
DUMP_REG(CRCA);
|
||||
DUMP_REG(CRCB);
|
||||
DUMP_REG(SEQ_CTL);
|
||||
DUMP_REG(LANE_SEQ_CTL);
|
||||
DUMP_REG(SEQ_INST(0));
|
||||
DUMP_REG(SEQ_INST(1));
|
||||
DUMP_REG(SEQ_INST(2));
|
||||
DUMP_REG(SEQ_INST(3));
|
||||
DUMP_REG(SEQ_INST(4));
|
||||
DUMP_REG(SEQ_INST(5));
|
||||
DUMP_REG(SEQ_INST(6));
|
||||
DUMP_REG(SEQ_INST(7));
|
||||
DUMP_REG(SEQ_INST(8));
|
||||
DUMP_REG(PWM_DIV);
|
||||
DUMP_REG(PWM_CTL);
|
||||
DUMP_REG(MSCHECK);
|
||||
DUMP_REG(XBAR_CTRL);
|
||||
DUMP_REG(DP_LINKCTL(0));
|
||||
DUMP_REG(DP_LINKCTL(1));
|
||||
DUMP_REG(DC(0));
|
||||
DUMP_REG(DC(1));
|
||||
DUMP_REG(LANE_DRIVE_CURRENT(0));
|
||||
DUMP_REG(PR(0));
|
||||
DUMP_REG(LANE4_PREEMPHASIS(0));
|
||||
DUMP_REG(POSTCURSOR(0));
|
||||
DUMP_REG(DP_CONFIG(0));
|
||||
DUMP_REG(DP_CONFIG(1));
|
||||
DUMP_REG(DP_MN(0));
|
||||
DUMP_REG(DP_MN(1));
|
||||
DUMP_REG(DP_PADCTL(0));
|
||||
DUMP_REG(DP_PADCTL(1));
|
||||
DUMP_REG(DP_DEBUG(0));
|
||||
DUMP_REG(DP_DEBUG(1));
|
||||
DUMP_REG(DP_SPARE(0));
|
||||
DUMP_REG(DP_SPARE(1));
|
||||
DUMP_REG(DP_TPG);
|
||||
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
|
||||
static void tegra_dc_sor_config_panel(struct tegra_dc_sor_data *sor,
|
||||
int is_lvds,
|
||||
const struct tegra_dp_link_config *link_cfg,
|
||||
const struct display_timing *timing)
|
||||
{
|
||||
const int head_num = 0;
|
||||
u32 reg_val = STATE1_ASY_OWNER_HEAD0 << head_num;
|
||||
u32 vtotal, htotal;
|
||||
u32 vsync_end, hsync_end;
|
||||
u32 vblank_end, hblank_end;
|
||||
u32 vblank_start, hblank_start;
|
||||
|
||||
reg_val |= is_lvds ? STATE1_ASY_PROTOCOL_LVDS_CUSTOM :
|
||||
STATE1_ASY_PROTOCOL_DP_A;
|
||||
reg_val |= STATE1_ASY_SUBOWNER_NONE |
|
||||
STATE1_ASY_CRCMODE_COMPLETE_RASTER;
|
||||
|
||||
reg_val |= STATE1_ASY_HSYNCPOL_NEGATIVE_TRUE;
|
||||
reg_val |= STATE1_ASY_VSYNCPOL_NEGATIVE_TRUE;
|
||||
reg_val |= (link_cfg->bits_per_pixel > 18) ?
|
||||
STATE1_ASY_PIXELDEPTH_BPP_24_444 :
|
||||
STATE1_ASY_PIXELDEPTH_BPP_18_444;
|
||||
|
||||
tegra_sor_writel(sor, STATE1, reg_val);
|
||||
|
||||
/*
|
||||
* Skipping programming NV_HEAD_STATE0, assuming:
|
||||
* interlacing: PROGRESSIVE, dynamic range: VESA, colorspace: RGB
|
||||
*/
|
||||
vtotal = timing->vsync_len.typ + timing->vback_porch.typ +
|
||||
timing->vactive.typ + timing->vfront_porch.typ;
|
||||
htotal = timing->hsync_len.typ + timing->hback_porch.typ +
|
||||
timing->hactive.typ + timing->hfront_porch.typ;
|
||||
|
||||
tegra_sor_writel(sor, NV_HEAD_STATE1(head_num),
|
||||
vtotal << NV_HEAD_STATE1_VTOTAL_SHIFT |
|
||||
htotal << NV_HEAD_STATE1_HTOTAL_SHIFT);
|
||||
|
||||
vsync_end = timing->vsync_len.typ - 1;
|
||||
hsync_end = timing->hsync_len.typ - 1;
|
||||
tegra_sor_writel(sor, NV_HEAD_STATE2(head_num),
|
||||
vsync_end << NV_HEAD_STATE2_VSYNC_END_SHIFT |
|
||||
hsync_end << NV_HEAD_STATE2_HSYNC_END_SHIFT);
|
||||
|
||||
vblank_end = vsync_end + timing->vback_porch.typ;
|
||||
hblank_end = hsync_end + timing->hback_porch.typ;
|
||||
tegra_sor_writel(sor, NV_HEAD_STATE3(head_num),
|
||||
vblank_end << NV_HEAD_STATE3_VBLANK_END_SHIFT |
|
||||
hblank_end << NV_HEAD_STATE3_HBLANK_END_SHIFT);
|
||||
|
||||
vblank_start = vblank_end + timing->vactive.typ;
|
||||
hblank_start = hblank_end + timing->hactive.typ;
|
||||
tegra_sor_writel(sor, NV_HEAD_STATE4(head_num),
|
||||
vblank_start << NV_HEAD_STATE4_VBLANK_START_SHIFT |
|
||||
hblank_start << NV_HEAD_STATE4_HBLANK_START_SHIFT);
|
||||
|
||||
/* TODO: adding interlace mode support */
|
||||
tegra_sor_writel(sor, NV_HEAD_STATE5(head_num), 0x1);
|
||||
|
||||
tegra_sor_write_field(sor, CSTM,
|
||||
CSTM_ROTCLK_DEFAULT_MASK |
|
||||
CSTM_LVDS_EN_ENABLE,
|
||||
2 << CSTM_ROTCLK_SHIFT |
|
||||
is_lvds ? CSTM_LVDS_EN_ENABLE :
|
||||
CSTM_LVDS_EN_DISABLE);
|
||||
|
||||
tegra_dc_sor_config_pwm(sor, 1024, 1024);
|
||||
}
|
||||
|
||||
static void tegra_dc_sor_enable_dc(struct dc_ctlr *disp_ctrl)
|
||||
{
|
||||
u32 reg_val = readl(&disp_ctrl->cmd.state_access);
|
||||
|
||||
writel(reg_val | WRITE_MUX_ACTIVE, &disp_ctrl->cmd.state_access);
|
||||
writel(VSYNC_H_POSITION(1), &disp_ctrl->disp.disp_timing_opt);
|
||||
|
||||
/* Enable DC now - otherwise pure text console may not show. */
|
||||
writel(CTRL_MODE_C_DISPLAY << CTRL_MODE_SHIFT,
|
||||
&disp_ctrl->cmd.disp_cmd);
|
||||
writel(reg_val, &disp_ctrl->cmd.state_access);
|
||||
}
|
||||
|
||||
int tegra_dc_sor_enable_dp(struct tegra_dc_sor_data *sor,
|
||||
const struct tegra_dp_link_config *link_cfg)
|
||||
{
|
||||
int ret;
|
||||
|
||||
tegra_sor_write_field(sor, CLK_CNTRL,
|
||||
CLK_CNTRL_DP_CLK_SEL_MASK,
|
||||
CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK);
|
||||
|
||||
tegra_sor_write_field(sor, PLL2,
|
||||
PLL2_AUX6_BANDGAP_POWERDOWN_MASK,
|
||||
PLL2_AUX6_BANDGAP_POWERDOWN_DISABLE);
|
||||
udelay(25);
|
||||
|
||||
tegra_sor_write_field(sor, PLL3,
|
||||
PLL3_PLLVDD_MODE_MASK,
|
||||
PLL3_PLLVDD_MODE_V3_3);
|
||||
tegra_sor_writel(sor, PLL0,
|
||||
0xf << PLL0_ICHPMP_SHFIT |
|
||||
0x3 << PLL0_VCOCAP_SHIFT |
|
||||
PLL0_PLLREG_LEVEL_V45 |
|
||||
PLL0_RESISTORSEL_EXT |
|
||||
PLL0_PWR_ON | PLL0_VCOPD_RESCIND);
|
||||
tegra_sor_write_field(sor, PLL2,
|
||||
PLL2_AUX1_SEQ_MASK |
|
||||
PLL2_AUX9_LVDSEN_OVERRIDE |
|
||||
PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_MASK,
|
||||
PLL2_AUX1_SEQ_PLLCAPPD_OVERRIDE |
|
||||
PLL2_AUX9_LVDSEN_OVERRIDE |
|
||||
PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_DISABLE);
|
||||
tegra_sor_writel(sor, PLL1, PLL1_TERM_COMPOUT_HIGH |
|
||||
PLL1_TMDS_TERM_ENABLE);
|
||||
|
||||
if (tegra_dc_sor_poll_register(sor, PLL2,
|
||||
PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_MASK,
|
||||
PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_DISABLE,
|
||||
100, TEGRA_SOR_TIMEOUT_MS)) {
|
||||
printf("DP failed to lock PLL\n");
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
tegra_sor_write_field(sor, PLL2, PLL2_AUX2_MASK |
|
||||
PLL2_AUX7_PORT_POWERDOWN_MASK,
|
||||
PLL2_AUX2_OVERRIDE_POWERDOWN |
|
||||
PLL2_AUX7_PORT_POWERDOWN_DISABLE);
|
||||
|
||||
ret = tegra_dc_sor_power_up(sor, 0);
|
||||
if (ret) {
|
||||
debug("DP failed to power up\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* re-enable SOR clock */
|
||||
clock_sor_enable_edp_clock();
|
||||
|
||||
/* Power up lanes */
|
||||
tegra_dc_sor_power_dplanes(sor, link_cfg->lane_count, 1);
|
||||
|
||||
tegra_dc_sor_set_dp_mode(sor, link_cfg);
|
||||
debug("%s ret\n", __func__);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int tegra_dc_sor_attach(struct tegra_dc_sor_data *sor,
|
||||
const struct tegra_dp_link_config *link_cfg,
|
||||
const struct display_timing *timing)
|
||||
{
|
||||
const void *blob = gd->fdt_blob;
|
||||
struct dc_ctlr *disp_ctrl;
|
||||
u32 reg_val;
|
||||
int node;
|
||||
|
||||
/* Use the first display controller */
|
||||
debug("%s\n", __func__);
|
||||
node = fdtdec_next_compatible(blob, 0, COMPAT_NVIDIA_TEGRA124_DC);
|
||||
if (node < 0)
|
||||
return -ENOENT;
|
||||
disp_ctrl = (struct dc_ctlr *)fdtdec_get_addr(blob, node, "reg");
|
||||
|
||||
tegra_dc_sor_enable_dc(disp_ctrl);
|
||||
tegra_dc_sor_config_panel(sor, 0, link_cfg, timing);
|
||||
|
||||
writel(0x9f00, &disp_ctrl->cmd.state_ctrl);
|
||||
writel(0x9f, &disp_ctrl->cmd.state_ctrl);
|
||||
|
||||
writel(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
|
||||
PW4_ENABLE | PM0_ENABLE | PM1_ENABLE,
|
||||
&disp_ctrl->cmd.disp_pow_ctrl);
|
||||
|
||||
reg_val = tegra_sor_readl(sor, TEST);
|
||||
if (reg_val & TEST_ATTACHED_TRUE)
|
||||
return -EEXIST;
|
||||
|
||||
tegra_sor_writel(sor, SUPER_STATE1,
|
||||
SUPER_STATE1_ATTACHED_NO);
|
||||
|
||||
/*
|
||||
* Enable display2sor clock at least 2 cycles before DC start,
|
||||
* to clear sor internal valid signal.
|
||||
*/
|
||||
writel(SOR_ENABLE, &disp_ctrl->disp.disp_win_opt);
|
||||
writel(GENERAL_ACT_REQ, &disp_ctrl->cmd.state_ctrl);
|
||||
writel(0, &disp_ctrl->disp.disp_win_opt);
|
||||
writel(GENERAL_ACT_REQ, &disp_ctrl->cmd.state_ctrl);
|
||||
|
||||
/* Attach head */
|
||||
tegra_dc_sor_update(sor);
|
||||
tegra_sor_writel(sor, SUPER_STATE1,
|
||||
SUPER_STATE1_ATTACHED_YES);
|
||||
tegra_sor_writel(sor, SUPER_STATE1,
|
||||
SUPER_STATE1_ATTACHED_YES |
|
||||
SUPER_STATE1_ASY_HEAD_OP_AWAKE |
|
||||
SUPER_STATE1_ASY_ORMODE_NORMAL);
|
||||
tegra_dc_sor_super_update(sor);
|
||||
|
||||
/* Enable dc */
|
||||
reg_val = readl(&disp_ctrl->cmd.state_access);
|
||||
writel(reg_val | WRITE_MUX_ACTIVE, &disp_ctrl->cmd.state_access);
|
||||
writel(CTRL_MODE_C_DISPLAY << CTRL_MODE_SHIFT,
|
||||
&disp_ctrl->cmd.disp_cmd);
|
||||
writel(SOR_ENABLE, &disp_ctrl->disp.disp_win_opt);
|
||||
writel(reg_val, &disp_ctrl->cmd.state_access);
|
||||
|
||||
if (tegra_dc_sor_poll_register(sor, TEST,
|
||||
TEST_ACT_HEAD_OPMODE_DEFAULT_MASK,
|
||||
TEST_ACT_HEAD_OPMODE_AWAKE,
|
||||
100,
|
||||
TEGRA_SOR_ATTACH_TIMEOUT_MS)) {
|
||||
printf("dc timeout waiting for OPMOD = AWAKE\n");
|
||||
return -ETIMEDOUT;
|
||||
} else {
|
||||
debug("%s: sor is attached\n", __func__);
|
||||
}
|
||||
|
||||
#if DEBUG_SOR
|
||||
dump_sor_reg(sor);
|
||||
#endif
|
||||
debug("%s: ret=%d\n", __func__, 0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void tegra_dc_sor_set_lane_parm(struct tegra_dc_sor_data *sor,
|
||||
const struct tegra_dp_link_config *link_cfg)
|
||||
{
|
||||
tegra_sor_writel(sor, LANE_DRIVE_CURRENT(sor->portnum),
|
||||
link_cfg->drive_current);
|
||||
tegra_sor_writel(sor, PR(sor->portnum),
|
||||
link_cfg->preemphasis);
|
||||
tegra_sor_writel(sor, POSTCURSOR(sor->portnum),
|
||||
link_cfg->postcursor);
|
||||
tegra_sor_writel(sor, LVDS, 0);
|
||||
|
||||
tegra_dc_sor_set_link_bandwidth(sor, link_cfg->link_bw);
|
||||
tegra_dc_sor_set_lane_count(sor, link_cfg->lane_count);
|
||||
|
||||
tegra_sor_write_field(sor, DP_PADCTL(sor->portnum),
|
||||
DP_PADCTL_TX_PU_ENABLE |
|
||||
DP_PADCTL_TX_PU_VALUE_DEFAULT_MASK,
|
||||
DP_PADCTL_TX_PU_ENABLE |
|
||||
2 << DP_PADCTL_TX_PU_VALUE_SHIFT);
|
||||
|
||||
/* Precharge */
|
||||
tegra_sor_write_field(sor, DP_PADCTL(sor->portnum), 0xf0, 0xf0);
|
||||
udelay(20);
|
||||
|
||||
tegra_sor_write_field(sor, DP_PADCTL(sor->portnum), 0xf0, 0x0);
|
||||
}
|
||||
|
||||
void tegra_dc_sor_power_down_unused_lanes(struct tegra_dc_sor_data *sor,
|
||||
const struct tegra_dp_link_config *link_cfg)
|
||||
{
|
||||
u32 pad_ctrl = 0;
|
||||
u32 drive_current = 0;
|
||||
u32 pre_emphasis = 0;
|
||||
int err = 0;
|
||||
|
||||
switch (link_cfg->lane_count) {
|
||||
case 4:
|
||||
pad_ctrl = DP_PADCTL_PD_TXD_0_NO |
|
||||
DP_PADCTL_PD_TXD_1_NO |
|
||||
DP_PADCTL_PD_TXD_2_NO |
|
||||
DP_PADCTL_PD_TXD_3_NO;
|
||||
break;
|
||||
case 2:
|
||||
pad_ctrl = DP_PADCTL_PD_TXD_0_NO |
|
||||
DP_PADCTL_PD_TXD_1_NO |
|
||||
DP_PADCTL_PD_TXD_2_YES |
|
||||
DP_PADCTL_PD_TXD_3_YES;
|
||||
break;
|
||||
case 1:
|
||||
pad_ctrl = DP_PADCTL_PD_TXD_0_NO |
|
||||
DP_PADCTL_PD_TXD_1_YES |
|
||||
DP_PADCTL_PD_TXD_2_YES |
|
||||
DP_PADCTL_PD_TXD_3_YES;
|
||||
break;
|
||||
default:
|
||||
printf("Invalid sor lane count: %u\n", link_cfg->lane_count);
|
||||
return;
|
||||
}
|
||||
|
||||
pad_ctrl |= DP_PADCTL_PAD_CAL_PD_POWERDOWN;
|
||||
tegra_sor_writel(sor, DP_PADCTL(sor->portnum), pad_ctrl);
|
||||
|
||||
err = tegra_dc_sor_enable_lane_sequencer(sor, 0, 0);
|
||||
if (err) {
|
||||
debug("Wait for lane power down failed: %d\n", err);
|
||||
return;
|
||||
}
|
||||
|
||||
/* Set to a known-good pre-calibrated setting */
|
||||
switch (link_cfg->link_bw) {
|
||||
case SOR_LINK_SPEED_G1_62:
|
||||
case SOR_LINK_SPEED_G2_7:
|
||||
drive_current = 0x13131313;
|
||||
pre_emphasis = 0;
|
||||
break;
|
||||
case SOR_LINK_SPEED_G5_4:
|
||||
drive_current = 0x19191919;
|
||||
pre_emphasis = 0x09090909;
|
||||
default:
|
||||
printf("Invalid sor link bandwidth: %d\n", link_cfg->link_bw);
|
||||
return;
|
||||
}
|
||||
|
||||
tegra_sor_writel(sor, LANE_DRIVE_CURRENT(sor->portnum),
|
||||
drive_current);
|
||||
tegra_sor_writel(sor, PR(sor->portnum), pre_emphasis);
|
||||
}
|
||||
|
||||
int tegra_dc_sor_init(struct tegra_dc_sor_data **sorp)
|
||||
{
|
||||
const void *blob = gd->fdt_blob;
|
||||
struct tegra_dc_sor_data *sor;
|
||||
int node;
|
||||
|
||||
node = fdtdec_next_compatible(blob, 0, COMPAT_NVIDIA_TEGRA124_SOR);
|
||||
if (node < 0)
|
||||
return -ENOENT;
|
||||
sor = calloc(1, sizeof(*sor));
|
||||
if (!sor)
|
||||
return -ENOMEM;
|
||||
sor->base = (void *)fdtdec_get_addr(blob, node, "reg");
|
||||
|
||||
node = fdtdec_next_compatible(blob, 0, COMPAT_NVIDIA_TEGRA124_PMC);
|
||||
if (node < 0)
|
||||
return -ENOENT;
|
||||
sor->pmc_base = (void *)fdtdec_get_addr(blob, node, "reg");
|
||||
|
||||
sor->power_is_up = 0;
|
||||
sor->portnum = 0;
|
||||
*sorp = sor;
|
||||
|
||||
return 0;
|
||||
}
|
||||
904
drivers/video/tegra124/sor.h
Normal file
904
drivers/video/tegra124/sor.h
Normal file
|
|
@ -0,0 +1,904 @@
|
|||
/*
|
||||
* Copyright (c) 2011-2013, NVIDIA Corporation.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
#ifndef _VIDEO_TEGRA124_SOR_H
|
||||
#define _VIDEO_TEGRA124_SOR_H
|
||||
|
||||
#define SUPER_STATE0 0x1
|
||||
#define SUPER_STATE0_UPDATE_SHIFT 0
|
||||
#define SUPER_STATE0_UPDATE_DEFAULT_MASK 0x1
|
||||
#define SUPER_STATE1 0x2
|
||||
#define SUPER_STATE1_ATTACHED_SHIFT 3
|
||||
#define SUPER_STATE1_ATTACHED_NO (0 << 3)
|
||||
#define SUPER_STATE1_ATTACHED_YES (1 << 3)
|
||||
#define SUPER_STATE1_ASY_ORMODE_SHIFT 2
|
||||
#define SUPER_STATE1_ASY_ORMODE_SAFE (0 << 2)
|
||||
#define SUPER_STATE1_ASY_ORMODE_NORMAL (1 << 2)
|
||||
#define SUPER_STATE1_ASY_HEAD_OP_SHIFT 0
|
||||
#define SUPER_STATE1_ASY_HEAD_OP_DEFAULT_MASK 0x3
|
||||
#define SUPER_STATE1_ASY_HEAD_OP_SLEEP 0
|
||||
#define SUPER_STATE1_ASY_HEAD_OP_SNOOZE 1
|
||||
#define SUPER_STATE1_ASY_HEAD_OP_AWAKE 2
|
||||
#define STATE0 0x3
|
||||
#define STATE0_UPDATE_SHIFT 0
|
||||
#define STATE0_UPDATE_DEFAULT_MASK 0x1
|
||||
#define STATE1 0x4
|
||||
#define STATE1_ASY_PIXELDEPTH_SHIFT 17
|
||||
#define STATE1_ASY_PIXELDEPTH_DEFAULT_MASK (0xf << 17)
|
||||
#define STATE1_ASY_PIXELDEPTH_BPP_16_422 (1 << 17)
|
||||
#define STATE1_ASY_PIXELDEPTH_BPP_18_444 (2 << 17)
|
||||
#define STATE1_ASY_PIXELDEPTH_BPP_20_422 (3 << 17)
|
||||
#define STATE1_ASY_PIXELDEPTH_BPP_24_422 (4 << 17)
|
||||
#define STATE1_ASY_PIXELDEPTH_BPP_24_444 (5 << 17)
|
||||
#define STATE1_ASY_PIXELDEPTH_BPP_30_444 (6 << 17)
|
||||
#define STATE1_ASY_PIXELDEPTH_BPP_32_422 (7 << 17)
|
||||
#define STATE1_ASY_PIXELDEPTH_BPP_36_444 (8 << 17)
|
||||
#define STATE1_ASY_PIXELDEPTH_BPP_48_444 (9 << 17)
|
||||
#define STATE1_ASY_REPLICATE_SHIFT 15
|
||||
#define STATE1_ASY_REPLICATE_DEFAULT_MASK (3 << 15)
|
||||
#define STATE1_ASY_REPLICATE_OFF (0 << 15)
|
||||
#define STATE1_ASY_REPLICATE_X2 (1 << 15)
|
||||
#define STATE1_ASY_REPLICATE_X4 (2 << 15)
|
||||
#define STATE1_ASY_DEPOL_SHIFT 14
|
||||
#define STATE1_ASY_DEPOL_DEFAULT_MASK (1 << 14)
|
||||
#define STATE1_ASY_DEPOL_POSITIVE_TRUE (0 << 14)
|
||||
#define STATE1_ASY_DEPOL_NEGATIVE_TRUE (1 << 14)
|
||||
#define STATE1_ASY_VSYNCPOL_SHIFT 13
|
||||
#define STATE1_ASY_VSYNCPOL_DEFAULT_MASK (1 << 13)
|
||||
#define STATE1_ASY_VSYNCPOL_POSITIVE_TRUE (0 << 13)
|
||||
#define STATE1_ASY_VSYNCPOL_NEGATIVE_TRUE (1 << 13)
|
||||
#define STATE1_ASY_HSYNCPOL_SHIFT 12
|
||||
#define STATE1_ASY_HSYNCPOL_DEFAULT_MASK (1 << 12)
|
||||
#define STATE1_ASY_HSYNCPOL_POSITIVE_TRUE (0 << 12)
|
||||
#define STATE1_ASY_HSYNCPOL_NEGATIVE_TRUE (1 << 12)
|
||||
#define STATE1_ASY_PROTOCOL_SHIFT 8
|
||||
#define STATE1_ASY_PROTOCOL_DEFAULT_MASK (0xf << 8)
|
||||
#define STATE1_ASY_PROTOCOL_LVDS_CUSTOM (0 << 8)
|
||||
#define STATE1_ASY_PROTOCOL_DP_A (8 << 8)
|
||||
#define STATE1_ASY_PROTOCOL_DP_B (9 << 8)
|
||||
#define STATE1_ASY_PROTOCOL_CUSTOM (15 << 8)
|
||||
#define STATE1_ASY_CRCMODE_SHIFT 6
|
||||
#define STATE1_ASY_CRCMODE_DEFAULT_MASK (3 << 6)
|
||||
#define STATE1_ASY_CRCMODE_ACTIVE_RASTER (0 << 6)
|
||||
#define STATE1_ASY_CRCMODE_COMPLETE_RASTER (1 << 6)
|
||||
#define STATE1_ASY_CRCMODE_NON_ACTIVE_RASTER (2 << 6)
|
||||
#define STATE1_ASY_SUBOWNER_SHIFT 4
|
||||
#define STATE1_ASY_SUBOWNER_DEFAULT_MASK (3 << 4)
|
||||
#define STATE1_ASY_SUBOWNER_NONE (0 << 4)
|
||||
#define STATE1_ASY_SUBOWNER_SUBHEAD0 (1 << 4)
|
||||
#define STATE1_ASY_SUBOWNER_SUBHEAD1 (2 << 4)
|
||||
#define STATE1_ASY_SUBOWNER_BOTH (3 << 4)
|
||||
#define STATE1_ASY_OWNER_SHIFT 0
|
||||
#define STATE1_ASY_OWNER_DEFAULT_MASK 0xf
|
||||
#define STATE1_ASY_OWNER_NONE 0
|
||||
#define STATE1_ASY_OWNER_HEAD0 1
|
||||
#define STATE1_ASY_OWNER_HEAD1 2
|
||||
#define NV_HEAD_STATE0(i) 0x5
|
||||
#define NV_HEAD_STATE0_INTERLACED_SHIFT 4
|
||||
#define NV_HEAD_STATE0_INTERLACED_DEFAULT_MASK (3 << 4)
|
||||
#define NV_HEAD_STATE0_INTERLACED_PROGRESSIVE (0 << 4)
|
||||
#define NV_HEAD_STATE0_INTERLACED_INTERLACED (1 << 4)
|
||||
#define NV_HEAD_STATE0_RANGECOMPRESS_SHIFT 3
|
||||
#define NV_HEAD_STATE0_RANGECOMPRESS_DEFAULT_MASK (1 << 3)
|
||||
#define NV_HEAD_STATE0_RANGECOMPRESS_DISABLE (0 << 3)
|
||||
#define NV_HEAD_STATE0_RANGECOMPRESS_ENABLE (1 << 3)
|
||||
#define NV_HEAD_STATE0_DYNRANGE_SHIFT 2
|
||||
#define NV_HEAD_STATE0_DYNRANGE_DEFAULT_MASK (1 << 2)
|
||||
#define NV_HEAD_STATE0_DYNRANGE_VESA (0 << 2)
|
||||
#define NV_HEAD_STATE0_DYNRANGE_CEA (1 << 2)
|
||||
#define NV_HEAD_STATE0_COLORSPACE_SHIFT 0
|
||||
#define NV_HEAD_STATE0_COLORSPACE_DEFAULT_MASK 0x3
|
||||
#define NV_HEAD_STATE0_COLORSPACE_RGB 0
|
||||
#define NV_HEAD_STATE0_COLORSPACE_YUV_601 1
|
||||
#define NV_HEAD_STATE0_COLORSPACE_YUV_709 2
|
||||
#define NV_HEAD_STATE1(i) (7 + i)
|
||||
#define NV_HEAD_STATE1_VTOTAL_SHIFT 16
|
||||
#define NV_HEAD_STATE1_VTOTAL_DEFAULT_MASK (0x7fff << 16)
|
||||
#define NV_HEAD_STATE1_HTOTAL_SHIFT 0
|
||||
#define NV_HEAD_STATE1_HTOTAL_DEFAULT_MASK 0x7fff
|
||||
#define NV_HEAD_STATE2(i) (9 + i)
|
||||
#define NV_HEAD_STATE2_VSYNC_END_SHIFT 16
|
||||
#define NV_HEAD_STATE2_VSYNC_END_DEFAULT_MASK (0x7fff << 16)
|
||||
#define NV_HEAD_STATE2_HSYNC_END_SHIFT 0
|
||||
#define NV_HEAD_STATE2_HSYNC_END_DEFAULT_MASK 0x7fff
|
||||
#define NV_HEAD_STATE3(i) (0xb + i)
|
||||
#define NV_HEAD_STATE3_VBLANK_END_SHIFT 16
|
||||
#define NV_HEAD_STATE3_VBLANK_END_DEFAULT_MASK (0x7fff << 16)
|
||||
#define NV_HEAD_STATE3_HBLANK_END_SHIFT 0
|
||||
#define NV_HEAD_STATE3_HBLANK_END_DEFAULT_MASK 0x7fff
|
||||
#define NV_HEAD_STATE4(i) (0xd + i)
|
||||
#define NV_HEAD_STATE4_VBLANK_START_SHIFT 16
|
||||
#define NV_HEAD_STATE4_VBLANK_START_DEFAULT_MASK (0x7fff << 16)
|
||||
#define NV_HEAD_STATE4_HBLANK_START_SHIFT 0
|
||||
#define NV_HEAD_STATE4_HBLANK_START_DEFAULT_MASK 0x7fff
|
||||
#define NV_HEAD_STATE5(i) (0xf + i)
|
||||
#define CRC_CNTRL 0x11
|
||||
#define CRC_CNTRL_ARM_CRC_ENABLE_SHIFT 0
|
||||
#define CRC_CNTRL_ARM_CRC_ENABLE_NO 0
|
||||
#define CRC_CNTRL_ARM_CRC_ENABLE_YES 1
|
||||
#define CRC_CNTRL_ARM_CRC_ENABLE_DIS 0
|
||||
#define CRC_CNTRL_ARM_CRC_ENABLE_EN 1
|
||||
#define CLK_CNTRL 0x13
|
||||
#define CLK_CNTRL_DP_CLK_SEL_SHIFT 0
|
||||
#define CLK_CNTRL_DP_CLK_SEL_MASK 0x3
|
||||
#define CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK 0
|
||||
#define CLK_CNTRL_DP_CLK_SEL_DIFF_PCLK 1
|
||||
#define CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK 2
|
||||
#define CLK_CNTRL_DP_CLK_SEL_DIFF_DPCLK 3
|
||||
#define CLK_CNTRL_DP_LINK_SPEED_SHIFT 2
|
||||
#define CLK_CNTRL_DP_LINK_SPEED_MASK (0x1f << 2)
|
||||
#define CLK_CNTRL_DP_LINK_SPEED_G1_62 (6 << 2)
|
||||
#define CLK_CNTRL_DP_LINK_SPEED_G2_7 (10 << 2)
|
||||
#define CLK_CNTRL_DP_LINK_SPEED_LVDS (7 << 2)
|
||||
#define CAP 0x14
|
||||
#define CAP_DP_A_SHIFT 24
|
||||
#define CAP_DP_A_DEFAULT_MASK (1 << 24)
|
||||
#define CAP_DP_A_FALSE (0 << 24)
|
||||
#define CAP_DP_A_TRUE (1 << 24)
|
||||
#define CAP_DP_B_SHIFT 25
|
||||
#define CAP_DP_B_DEFAULT_MASK (1 << 24)
|
||||
#define CAP_DP_B_FALSE (0 << 24)
|
||||
#define CAP_DP_B_TRUE (1 << 24)
|
||||
#define PWR 0x15
|
||||
#define PWR_SETTING_NEW_SHIFT 31
|
||||
#define PWR_SETTING_NEW_DEFAULT_MASK (1 << 31)
|
||||
#define PWR_SETTING_NEW_DONE (0 << 31)
|
||||
#define PWR_SETTING_NEW_PENDING (1 << 31)
|
||||
#define PWR_SETTING_NEW_TRIGGER (1 << 31)
|
||||
#define PWR_MODE_SHIFT 28
|
||||
#define PWR_MODE_DEFAULT_MASK (1 << 28)
|
||||
#define PWR_MODE_NORMAL (0 << 28)
|
||||
#define PWR_MODE_SAFE (1 << 28)
|
||||
#define PWR_HALT_DELAY_SHIFT 24
|
||||
#define PWR_HALT_DELAY_DEFAULT_MASK (1 << 24)
|
||||
#define PWR_HALT_DELAY_DONE (0 << 24)
|
||||
#define PWR_HALT_DELAY_ACTIVE (1 << 24)
|
||||
#define PWR_SAFE_START_SHIFT 17
|
||||
#define PWR_SAFE_START_DEFAULT_MASK (1 << 17)
|
||||
#define PWR_SAFE_START_NORMAL (0 << 17)
|
||||
#define PWR_SAFE_START_ALT (1 << 17)
|
||||
#define PWR_SAFE_STATE_SHIFT 16
|
||||
#define PWR_SAFE_STATE_DEFAULT_MASK (1 << 16)
|
||||
#define PWR_SAFE_STATE_PD (0 << 16)
|
||||
#define PWR_SAFE_STATE_PU (1 << 16)
|
||||
#define PWR_NORMAL_START_SHIFT 1
|
||||
#define PWR_NORMAL_START_DEFAULT_MASK (1 << 1)
|
||||
#define PWR_NORMAL_START_NORMAL (0 << 16)
|
||||
#define PWR_NORMAL_START_ALT (1 << 16)
|
||||
#define PWR_NORMAL_STATE_SHIFT 0
|
||||
#define PWR_NORMAL_STATE_DEFAULT_MASK 0x1
|
||||
#define PWR_NORMAL_STATE_PD 0
|
||||
#define PWR_NORMAL_STATE_PU 1
|
||||
#define TEST 0x16
|
||||
#define TEST_TESTMUX_SHIFT 24
|
||||
#define TEST_TESTMUX_DEFAULT_MASK (0xff << 24)
|
||||
#define TEST_TESTMUX_AVSS (0 << 24)
|
||||
#define TEST_TESTMUX_CLOCKIN (2 << 24)
|
||||
#define TEST_TESTMUX_PLL_VOL (4 << 24)
|
||||
#define TEST_TESTMUX_SLOWCLKINT (8 << 24)
|
||||
#define TEST_TESTMUX_AVDD (16 << 24)
|
||||
#define TEST_TESTMUX_VDDREG (32 << 24)
|
||||
#define TEST_TESTMUX_REGREF_VDDREG (64 << 24)
|
||||
#define TEST_TESTMUX_REGREF_AVDD (128 << 24)
|
||||
#define TEST_CRC_SHIFT 23
|
||||
#define TEST_CRC_PRE_SERIALIZE (0 << 23)
|
||||
#define TEST_CRC_POST_DESERIALIZE (1 << 23)
|
||||
#define TEST_TPAT_SHIFT 20
|
||||
#define TEST_TPAT_DEFAULT_MASK (7 << 20)
|
||||
#define TEST_TPAT_LO (0 << 20)
|
||||
#define TEST_TPAT_TDAT (1 << 20)
|
||||
#define TEST_TPAT_RAMP (2 << 20)
|
||||
#define TEST_TPAT_WALK (3 << 20)
|
||||
#define TEST_TPAT_MAXSTEP (4 << 20)
|
||||
#define TEST_TPAT_MINSTEP (5 << 20)
|
||||
#define TEST_DSRC_SHIFT 16
|
||||
#define TEST_DSRC_DEFAULT_MASK (3 << 16)
|
||||
#define TEST_DSRC_NORMAL (0 << 16)
|
||||
#define TEST_DSRC_DEBUG (1 << 16)
|
||||
#define TEST_DSRC_TGEN (2 << 16)
|
||||
#define TEST_HEAD_NUMBER_SHIFT 12
|
||||
#define TEST_HEAD_NUMBER_DEFAULT_MASK (3 << 12)
|
||||
#define TEST_HEAD_NUMBER_NONE (0 << 12)
|
||||
#define TEST_HEAD_NUMBER_HEAD0 (1 << 12)
|
||||
#define TEST_HEAD_NUMBER_HEAD1 (2 << 12)
|
||||
#define TEST_ATTACHED_SHIFT 10
|
||||
#define TEST_ATTACHED_DEFAULT_MASK (1 << 10)
|
||||
#define TEST_ATTACHED_FALSE (0 << 10)
|
||||
#define TEST_ATTACHED_TRUE (1 << 10)
|
||||
#define TEST_ACT_HEAD_OPMODE_SHIFT 8
|
||||
#define TEST_ACT_HEAD_OPMODE_DEFAULT_MASK (3 << 8)
|
||||
#define TEST_ACT_HEAD_OPMODE_SLEEP (0 << 8)
|
||||
#define TEST_ACT_HEAD_OPMODE_SNOOZE (1 << 8)
|
||||
#define TEST_ACT_HEAD_OPMODE_AWAKE (2 << 8)
|
||||
#define TEST_INVD_SHIFT 6
|
||||
#define TEST_INVD_DISABLE (0 << 6)
|
||||
#define TEST_INVD_ENABLE (1 << 6)
|
||||
#define TEST_TEST_ENABLE_SHIFT 1
|
||||
#define TEST_TEST_ENABLE_DISABLE (0 << 1)
|
||||
#define TEST_TEST_ENABLE_ENABLE (1 << 1)
|
||||
#define PLL0 0x17
|
||||
#define PLL0_ICHPMP_SHFIT 24
|
||||
#define PLL0_ICHPMP_DEFAULT_MASK (0xf << 24)
|
||||
#define PLL0_VCOCAP_SHIFT 8
|
||||
#define PLL0_VCOCAP_DEFAULT_MASK (0xf << 8)
|
||||
#define PLL0_PLLREG_LEVEL_SHIFT 6
|
||||
#define PLL0_PLLREG_LEVEL_DEFAULT_MASK (3 << 6)
|
||||
#define PLL0_PLLREG_LEVEL_V25 (0 << 6)
|
||||
#define PLL0_PLLREG_LEVEL_V15 (1 << 6)
|
||||
#define PLL0_PLLREG_LEVEL_V35 (2 << 6)
|
||||
#define PLL0_PLLREG_LEVEL_V45 (3 << 6)
|
||||
#define PLL0_PULLDOWN_SHIFT 5
|
||||
#define PLL0_PULLDOWN_DEFAULT_MASK (1 << 5)
|
||||
#define PLL0_PULLDOWN_DISABLE (0 << 5)
|
||||
#define PLL0_PULLDOWN_ENABLE (1 << 5)
|
||||
#define PLL0_RESISTORSEL_SHIFT 4
|
||||
#define PLL0_RESISTORSEL_DEFAULT_MASK (1 << 4)
|
||||
#define PLL0_RESISTORSEL_INT (0 << 4)
|
||||
#define PLL0_RESISTORSEL_EXT (1 << 4)
|
||||
#define PLL0_VCOPD_SHIFT 2
|
||||
#define PLL0_VCOPD_MASK (1 << 2)
|
||||
#define PLL0_VCOPD_RESCIND (0 << 2)
|
||||
#define PLL0_VCOPD_ASSERT (1 << 2)
|
||||
#define PLL0_PWR_SHIFT 0
|
||||
#define PLL0_PWR_MASK 1
|
||||
#define PLL0_PWR_ON 0
|
||||
#define PLL0_PWR_OFF 1
|
||||
#define PLL1_TMDS_TERM_SHIFT 8
|
||||
#define PLL1_TMDS_TERM_DISABLE (0 << 8)
|
||||
#define PLL1_TMDS_TERM_ENABLE (1 << 8)
|
||||
#define PLL1 0x18
|
||||
#define PLL1_TERM_COMPOUT_SHIFT 15
|
||||
#define PLL1_TERM_COMPOUT_LOW (0 << 15)
|
||||
#define PLL1_TERM_COMPOUT_HIGH (1 << 15)
|
||||
#define PLL2 0x19
|
||||
#define PLL2_DCIR_PLL_RESET_SHIFT 0
|
||||
#define PLL2_DCIR_PLL_RESET_OVERRIDE (0 << 0)
|
||||
#define PLL2_DCIR_PLL_RESET_ALLOW (1 << 0)
|
||||
#define PLL2_AUX1_SHIFT 17
|
||||
#define PLL2_AUX1_SEQ_MASK (1 << 17)
|
||||
#define PLL2_AUX1_SEQ_PLLCAPPD_ALLOW (0 << 17)
|
||||
#define PLL2_AUX1_SEQ_PLLCAPPD_OVERRIDE (1 << 17)
|
||||
#define PLL2_AUX2_SHIFT 18
|
||||
#define PLL2_AUX2_MASK (1 << 18)
|
||||
#define PLL2_AUX2_OVERRIDE_POWERDOWN (0 << 18)
|
||||
#define PLL2_AUX2_ALLOW_POWERDOWN (1 << 18)
|
||||
#define PLL2_AUX6_SHIFT 22
|
||||
#define PLL2_AUX6_BANDGAP_POWERDOWN_MASK (1 << 22)
|
||||
#define PLL2_AUX6_BANDGAP_POWERDOWN_DISABLE (0 << 22)
|
||||
#define PLL2_AUX6_BANDGAP_POWERDOWN_ENABLE (1 << 22)
|
||||
#define PLL2_AUX7_SHIFT 23
|
||||
#define PLL2_AUX7_PORT_POWERDOWN_MASK (1 << 23)
|
||||
#define PLL2_AUX7_PORT_POWERDOWN_DISABLE (0 << 23)
|
||||
#define PLL2_AUX7_PORT_POWERDOWN_ENABLE (1 << 23)
|
||||
#define PLL2_AUX8_SHIFT 24
|
||||
#define PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_MASK (1 << 24)
|
||||
#define PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_DISABLE (0 << 24)
|
||||
#define PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_ENABLE (1 << 24)
|
||||
#define PLL2_AUX9_SHIFT 25
|
||||
#define PLL2_AUX9_LVDSEN_ALLOW (0 << 25)
|
||||
#define PLL2_AUX9_LVDSEN_OVERRIDE (1 << 25)
|
||||
#define PLL3 0x1a
|
||||
#define PLL3_PLLVDD_MODE_SHIFT 13
|
||||
#define PLL3_PLLVDD_MODE_MASK (1 << 13)
|
||||
#define PLL3_PLLVDD_MODE_V1_8 (0 << 13)
|
||||
#define PLL3_PLLVDD_MODE_V3_3 (1 << 13)
|
||||
#define CSTM 0x1b
|
||||
#define CSTM_ROTDAT_SHIFT 28
|
||||
#define CSTM_ROTDAT_DEFAULT_MASK (7 << 28)
|
||||
#define CSTM_ROTCLK_SHIFT 24
|
||||
#define CSTM_ROTCLK_DEFAULT_MASK (0xf << 24)
|
||||
#define CSTM_LVDS_EN_SHIFT 16
|
||||
#define CSTM_LVDS_EN_DISABLE (0 << 16)
|
||||
#define CSTM_LVDS_EN_ENABLE (1 << 16)
|
||||
#define CSTM_LINKACTB_SHIFT 15
|
||||
#define CSTM_LINKACTB_DISABLE (0 << 15)
|
||||
#define CSTM_LINKACTB_ENABLE (1 << 15)
|
||||
#define CSTM_LINKACTA_SHIFT 14
|
||||
#define CSTM_LINKACTA_DISABLE (0 << 14)
|
||||
#define CSTM_LINKACTA_ENABLE (1 << 14)
|
||||
#define LVDS 0x1c
|
||||
#define LVDS_ROTDAT_SHIFT 28
|
||||
#define LVDS_ROTDAT_DEFAULT_MASK (7 << 28)
|
||||
#define LVDS_ROTDAT_RST (0 << 28)
|
||||
#define LVDS_ROTCLK_SHIFT 24
|
||||
#define LVDS_ROTCLK_DEFAULT_MASK (0xf << 24)
|
||||
#define LVDS_ROTCLK_RST (0 << 24)
|
||||
#define LVDS_PLLDIV_SHIFT 21
|
||||
#define LVDS_PLLDIV_DEFAULT_MASK (1 << 21)
|
||||
#define LVDS_PLLDIV_BY_7 (0 << 21)
|
||||
#define LVDS_BALANCED_SHIFT 19
|
||||
#define LVDS_BALANCED_DEFAULT_MASK (1 << 19)
|
||||
#define LVDS_BALANCED_DISABLE (0 << 19)
|
||||
#define LVDS_BALANCED_ENABLE (1 << 19)
|
||||
#define LVDS_NEW_MODE_SHIFT 18
|
||||
#define LVDS_NEW_MODE_DEFAULT_MASK (1 << 18)
|
||||
#define LVDS_NEW_MODE_DISABLE (0 << 18)
|
||||
#define LVDS_NEW_MODE_ENABLE (1 << 18)
|
||||
#define LVDS_DUP_SYNC_SHIFT 17
|
||||
#define LVDS_DUP_SYNC_DEFAULT_MASK (1 << 17)
|
||||
#define LVDS_DUP_SYNC_DISABLE (0 << 17)
|
||||
#define LVDS_DUP_SYNC_ENABLE (1 << 17)
|
||||
#define LVDS_LVDS_EN_SHIFT 16
|
||||
#define LVDS_LVDS_EN_DEFAULT_MASK (1 << 16)
|
||||
#define LVDS_LVDS_EN_ENABLE (1 << 16)
|
||||
#define LVDS_LINKACTB_SHIFT 15
|
||||
#define LVDS_LINKACTB_DEFAULT_MASK (1 << 15)
|
||||
#define LVDS_LINKACTB_DISABLE (0 << 15)
|
||||
#define LVDS_LINKACTB_ENABLE (1 << 15)
|
||||
#define LVDS_LINKACTA_SHIFT 14
|
||||
#define LVDS_LINKACTA_DEFAULT_MASK (1 << 14)
|
||||
#define LVDS_LINKACTA_ENABLE (1 << 14)
|
||||
#define LVDS_MODE_SHIFT 12
|
||||
#define LVDS_MODE_DEFAULT_MASK (3 << 12)
|
||||
#define LVDS_MODE_LVDS (0 << 12)
|
||||
#define LVDS_UPPER_SHIFT 11
|
||||
#define LVDS_UPPER_DEFAULT_MASK (1 << 11)
|
||||
#define LVDS_UPPER_FALSE (0 << 11)
|
||||
#define LVDS_UPPER_TRUE (1 << 11)
|
||||
#define LVDS_PD_TXCB_SHIFT 9
|
||||
#define LVDS_PD_TXCB_DEFAULT_MASK (1 << 9)
|
||||
#define LVDS_PD_TXCB_ENABLE (0 << 9)
|
||||
#define LVDS_PD_TXCB_DISABLE (1 << 9)
|
||||
#define LVDS_PD_TXCA_SHIFT 8
|
||||
#define LVDS_PD_TXCA_DEFAULT_MASK (1 << 8)
|
||||
#define LVDS_PD_TXCA_ENABLE (0 << 8)
|
||||
#define LVDS_PD_TXDB_3_SHIFT 7
|
||||
#define LVDS_PD_TXDB_3_DEFAULT_MASK (1 << 7)
|
||||
#define LVDS_PD_TXDB_3_ENABLE (0 << 7)
|
||||
#define LVDS_PD_TXDB_3_DISABLE (1 << 7)
|
||||
#define LVDS_PD_TXDB_2_SHIFT 6
|
||||
#define LVDS_PD_TXDB_2_DEFAULT_MASK (1 << 6)
|
||||
#define LVDS_PD_TXDB_2_ENABLE (0 << 6)
|
||||
#define LVDS_PD_TXDB_2_DISABLE (1 << 6)
|
||||
#define LVDS_PD_TXDB_1_SHIFT 5
|
||||
#define LVDS_PD_TXDB_1_DEFAULT_MASK (1 << 5)
|
||||
#define LVDS_PD_TXDB_1_ENABLE (0 << 5)
|
||||
#define LVDS_PD_TXDB_1_DISABLE (1 << 5)
|
||||
#define LVDS_PD_TXDB_0_SHIFT 4
|
||||
#define LVDS_PD_TXDB_0_DEFAULT_MASK (1 << 4)
|
||||
#define LVDS_PD_TXDB_0_ENABLE (0 << 4)
|
||||
#define LVDS_PD_TXDB_0_DISABLE (1 << 4)
|
||||
#define LVDS_PD_TXDA_3_SHIFT 3
|
||||
#define LVDS_PD_TXDA_3_DEFAULT_MASK (1 << 3)
|
||||
#define LVDS_PD_TXDA_3_ENABLE (0 << 3)
|
||||
#define LVDS_PD_TXDA_3_DISABLE (1 << 3)
|
||||
#define LVDS_PD_TXDA_2_SHIFT 2
|
||||
#define LVDS_PD_TXDA_2_DEFAULT_MASK (1 << 2)
|
||||
#define LVDS_PD_TXDA_2_ENABLE (0 << 2)
|
||||
#define LVDS_PD_TXDA_1_SHIFT 1
|
||||
#define LVDS_PD_TXDA_1_DEFAULT_MASK (1 << 1)
|
||||
#define LVDS_PD_TXDA_1_ENABLE (0 << 1)
|
||||
#define LVDS_PD_TXDA_0_SHIFT 0
|
||||
#define LVDS_PD_TXDA_0_DEFAULT_MASK 0x1
|
||||
#define LVDS_PD_TXDA_0_ENABLE 0
|
||||
#define CRCA 0x1d
|
||||
#define CRCA_VALID_FALSE 0
|
||||
#define CRCA_VALID_TRUE 1
|
||||
#define CRCA_VALID_RST 1
|
||||
#define CRCB 0x1e
|
||||
#define CRCB_CRC_DEFAULT_MASK 0xffffffff
|
||||
#define SEQ_CTL 0x20
|
||||
#define SEQ_CTL_SWITCH_SHIFT 30
|
||||
#define SEQ_CTL_SWITCH_MASK (1 << 30)
|
||||
#define SEQ_CTL_SWITCH_WAIT (0 << 30)
|
||||
#define SEQ_CTL_SWITCH_FORCE (1 << 30)
|
||||
#define SEQ_CTL_STATUS_SHIFT 28
|
||||
#define SEQ_CTL_STATUS_MASK (1 << 28)
|
||||
#define SEQ_CTL_STATUS_STOPPED (0 << 28)
|
||||
#define SEQ_CTL_STATUS_RUNNING (1 << 28)
|
||||
#define SEQ_CTL_PC_SHIFT 16
|
||||
#define SEQ_CTL_PC_MASK (0xf << 16)
|
||||
#define SEQ_CTL_PD_PC_ALT_SHIFT 12
|
||||
#define SEQ_CTL_PD_PC_ALT_MASK (0xf << 12)
|
||||
#define SEQ_CTL_PD_PC_SHIFT 8
|
||||
#define SEQ_CTL_PD_PC_MASK (0xf << 8)
|
||||
#define SEQ_CTL_PU_PC_ALT_SHIFT 4
|
||||
#define SEQ_CTL_PU_PC_ALT_MASK (0xf << 4)
|
||||
#define SEQ_CTL_PU_PC_SHIFT 0
|
||||
#define SEQ_CTL_PU_PC_MASK 0xf
|
||||
#define LANE_SEQ_CTL 0x21
|
||||
#define LANE_SEQ_CTL_SETTING_NEW_SHIFT 31
|
||||
#define LANE_SEQ_CTL_SETTING_MASK (1 << 31)
|
||||
#define LANE_SEQ_CTL_SETTING_NEW_DONE (0 << 31)
|
||||
#define LANE_SEQ_CTL_SETTING_NEW_PENDING (1 << 31)
|
||||
#define LANE_SEQ_CTL_SETTING_NEW_TRIGGER (1 << 31)
|
||||
#define LANE_SEQ_CTL_SEQ_STATE_SHIFT 28
|
||||
#define LANE_SEQ_CTL_SEQ_STATE_IDLE (0 << 28)
|
||||
#define LANE_SEQ_CTL_SEQ_STATE_BUSY (1 << 28)
|
||||
#define LANE_SEQ_CTL_SEQUENCE_SHIFT 20
|
||||
#define LANE_SEQ_CTL_SEQUENCE_UP (0 << 20)
|
||||
#define LANE_SEQ_CTL_SEQUENCE_DOWN (1 << 20)
|
||||
#define LANE_SEQ_CTL_NEW_POWER_STATE_SHIFT 16
|
||||
#define LANE_SEQ_CTL_NEW_POWER_STATE_PU (0 << 16)
|
||||
#define LANE_SEQ_CTL_NEW_POWER_STATE_PD (1 << 16)
|
||||
#define LANE_SEQ_CTL_DELAY_SHIFT 12
|
||||
#define LANE_SEQ_CTL_DELAY_DEFAULT_MASK (0xf << 12)
|
||||
#define LANE_SEQ_CTL_LANE9_STATE_SHIFT 9
|
||||
#define LANE_SEQ_CTL_LANE9_STATE_POWERUP (0 << 9)
|
||||
#define LANE_SEQ_CTL_LANE9_STATE_POWERDOWN (1 << 9)
|
||||
#define LANE_SEQ_CTL_LANE8_STATE_SHIFT 8
|
||||
#define LANE_SEQ_CTL_LANE8_STATE_POWERUP (0 << 8)
|
||||
#define LANE_SEQ_CTL_LANE8_STATE_POWERDOWN (1 << 8)
|
||||
#define LANE_SEQ_CTL_LANE7_STATE_SHIFT 7
|
||||
#define LANE_SEQ_CTL_LANE7_STATE_POWERUP (0 << 7)
|
||||
#define LANE_SEQ_CTL_LANE7_STATE_POWERDOWN (1 << 7)
|
||||
#define LANE_SEQ_CTL_LANE6_STATE_SHIFT 6
|
||||
#define LANE_SEQ_CTL_LANE6_STATE_POWERUP (0 << 6)
|
||||
#define LANE_SEQ_CTL_LANE6_STATE_POWERDOWN (1 << 6)
|
||||
#define LANE_SEQ_CTL_LANE5_STATE_SHIFT 5
|
||||
#define LANE_SEQ_CTL_LANE5_STATE_POWERUP (0 << 5)
|
||||
#define LANE_SEQ_CTL_LANE5_STATE_POWERDOWN (1 << 5)
|
||||
#define LANE_SEQ_CTL_LANE4_STATE_SHIFT 4
|
||||
#define LANE_SEQ_CTL_LANE4_STATE_POWERUP (0 << 4)
|
||||
#define LANE_SEQ_CTL_LANE4_STATE_POWERDOWN (1 << 4)
|
||||
#define LANE_SEQ_CTL_LANE3_STATE_SHIFT 3
|
||||
#define LANE_SEQ_CTL_LANE3_STATE_POWERUP (0 << 3)
|
||||
#define LANE_SEQ_CTL_LANE3_STATE_POWERDOWN (1 << 3)
|
||||
#define LANE_SEQ_CTL_LANE2_STATE_SHIFT 2
|
||||
#define LANE_SEQ_CTL_LANE2_STATE_POWERUP (0 << 2)
|
||||
#define LANE_SEQ_CTL_LANE2_STATE_POWERDOWN (1 << 2)
|
||||
#define LANE_SEQ_CTL_LANE1_STATE_SHIFT 1
|
||||
#define LANE_SEQ_CTL_LANE1_STATE_POWERUP (0 << 1)
|
||||
#define LANE_SEQ_CTL_LANE1_STATE_POWERDOWN (1 << 1)
|
||||
#define LANE_SEQ_CTL_LANE0_STATE_SHIFT 0
|
||||
#define LANE_SEQ_CTL_LANE0_STATE_POWERUP 0
|
||||
#define LANE_SEQ_CTL_LANE0_STATE_POWERDOWN 1
|
||||
#define SEQ_INST(i) (0x22 + i)
|
||||
#define SEQ_INST_PLL_PULLDOWN_SHIFT 31
|
||||
#define SEQ_INST_PLL_PULLDOWN_DISABLE (0 << 31)
|
||||
#define SEQ_INST_PLL_PULLDOWN_ENABLE (1 << 31)
|
||||
#define SEQ_INST_POWERDOWN_MACRO_SHIFT 30
|
||||
#define SEQ_INST_POWERDOWN_MACRO_NORMAL (0 << 30)
|
||||
#define SEQ_INST_POWERDOWN_MACRO_POWERDOWN (1 << 30)
|
||||
#define SEQ_INST_ASSERT_PLL_RESET_SHIFT 29
|
||||
#define SEQ_INST_ASSERT_PLL_RESET_NORMAL (0 << 29)
|
||||
#define SEQ_INST_ASSERT_PLL_RESET_RST (1 << 29)
|
||||
#define SEQ_INST_BLANK_V_SHIFT 28
|
||||
#define SEQ_INST_BLANK_V_NORMAL (0 << 28)
|
||||
#define SEQ_INST_BLANK_V_INACTIVE (1 << 28)
|
||||
#define SEQ_INST_BLANK_H_SHIFT 27
|
||||
#define SEQ_INST_BLANK_H_NORMAL (0 << 27)
|
||||
#define SEQ_INST_BLANK_H_INACTIVE (1 << 27)
|
||||
#define SEQ_INST_BLANK_DE_SHIFT 26
|
||||
#define SEQ_INST_BLANK_DE_NORMAL (0 << 26)
|
||||
#define SEQ_INST_BLANK_DE_INACTIVE (1 << 26)
|
||||
#define SEQ_INST_BLACK_DATA_SHIFT 25
|
||||
#define SEQ_INST_BLACK_DATA_NORMAL (0 << 25)
|
||||
#define SEQ_INST_BLACK_DATA_BLACK (1 << 25)
|
||||
#define SEQ_INST_TRISTATE_IOS_SHIFT 24
|
||||
#define SEQ_INST_TRISTATE_IOS_ENABLE_PINS (0 << 24)
|
||||
#define SEQ_INST_TRISTATE_IOS_TRISTATE (1 << 24)
|
||||
#define SEQ_INST_DRIVE_PWM_OUT_LO_SHIFT 23
|
||||
#define SEQ_INST_DRIVE_PWM_OUT_LO_FALSE (0 << 23)
|
||||
#define SEQ_INST_DRIVE_PWM_OUT_LO_TRUE (1 << 23)
|
||||
#define SEQ_INST_PIN_B_SHIFT 22
|
||||
#define SEQ_INST_PIN_B_LOW (0 << 22)
|
||||
#define SEQ_INST_PIN_B_HIGH (1 << 22)
|
||||
#define SEQ_INST_PIN_A_SHIFT 21
|
||||
#define SEQ_INST_PIN_A_LOW (0 << 21)
|
||||
#define SEQ_INST_PIN_A_HIGH (1 << 21)
|
||||
#define SEQ_INST_SEQUENCE_SHIFT 19
|
||||
#define SEQ_INST_SEQUENCE_UP (0 << 19)
|
||||
#define SEQ_INST_SEQUENCE_DOWN (1 << 19)
|
||||
#define SEQ_INST_LANE_SEQ_SHIFT 18
|
||||
#define SEQ_INST_LANE_SEQ_STOP (0 << 18)
|
||||
#define SEQ_INST_LANE_SEQ_RUN (1 << 18)
|
||||
#define SEQ_INST_PDPORT_SHIFT 17
|
||||
#define SEQ_INST_PDPORT_NO (0 << 17)
|
||||
#define SEQ_INST_PDPORT_YES (1 << 17)
|
||||
#define SEQ_INST_PDPLL_SHIFT 16
|
||||
#define SEQ_INST_PDPLL_NO (0 << 16)
|
||||
#define SEQ_INST_PDPLL_YES (1 << 16)
|
||||
#define SEQ_INST_HALT_SHIFT 15
|
||||
#define SEQ_INST_HALT_FALSE (0 << 15)
|
||||
#define SEQ_INST_HALT_TRUE (1 << 15)
|
||||
#define SEQ_INST_WAIT_UNITS_SHIFT 12
|
||||
#define SEQ_INST_WAIT_UNITS_DEFAULT_MASK (3 << 12)
|
||||
#define SEQ_INST_WAIT_UNITS_US (0 << 12)
|
||||
#define SEQ_INST_WAIT_UNITS_MS (1 << 12)
|
||||
#define SEQ_INST_WAIT_UNITS_VSYNC (2 << 12)
|
||||
#define SEQ_INST_WAIT_TIME_SHIFT 0
|
||||
#define SEQ_INST_WAIT_TIME_DEFAULT_MASK 0x3ff
|
||||
#define PWM_DIV 0x32
|
||||
#define PWM_DIV_DIVIDE_DEFAULT_MASK 0xffffff
|
||||
#define PWM_CTL 0x33
|
||||
#define PWM_CTL_SETTING_NEW_SHIFT 31
|
||||
#define PWM_CTL_SETTING_NEW_DONE (0 << 31)
|
||||
#define PWM_CTL_SETTING_NEW_PENDING (1 << 31)
|
||||
#define PWM_CTL_SETTING_NEW_TRIGGER (1 << 31)
|
||||
#define PWM_CTL_CLKSEL_SHIFT 30
|
||||
#define PWM_CTL_CLKSEL_PCLK (0 << 30)
|
||||
#define PWM_CTL_CLKSEL_XTAL (1 << 30)
|
||||
#define PWM_CTL_DUTY_CYCLE_SHIFT 0
|
||||
#define PWM_CTL_DUTY_CYCLE_MASK 0xffffff
|
||||
#define MSCHECK 0x49
|
||||
#define MSCHECK_CTL_SHIFT 31
|
||||
#define MSCHECK_CTL_CLEAR (0 << 31)
|
||||
#define MSCHECK_CTL_RUN (1 << 31)
|
||||
#define XBAR_CTRL 0x4a
|
||||
#define DP_LINKCTL(i) (0x4c + (i))
|
||||
#define DP_LINKCTL_FORCE_IDLEPTTRN_SHIFT 31
|
||||
#define DP_LINKCTL_FORCE_IDLEPTTRN_NO (0 << 31)
|
||||
#define DP_LINKCTL_FORCE_IDLEPTTRN_YES (1 << 31)
|
||||
#define DP_LINKCTL_COMPLIANCEPTTRN_SHIFT 28
|
||||
#define DP_LINKCTL_COMPLIANCEPTTRN_NOPATTERN (0 << 28)
|
||||
#define DP_LINKCTL_COMPLIANCEPTTRN_COLORSQARE (1 << 28)
|
||||
#define DP_LINKCTL_LANECOUNT_SHIFT 16
|
||||
#define DP_LINKCTL_LANECOUNT_MASK (0x1f << 16)
|
||||
#define DP_LINKCTL_LANECOUNT_ZERO (0 << 16)
|
||||
#define DP_LINKCTL_LANECOUNT_ONE (1 << 16)
|
||||
#define DP_LINKCTL_LANECOUNT_TWO (3 << 16)
|
||||
#define DP_LINKCTL_LANECOUNT_FOUR (15 << 16)
|
||||
#define DP_LINKCTL_ENHANCEDFRAME_SHIFT 14
|
||||
#define DP_LINKCTL_ENHANCEDFRAME_DISABLE (0 << 14)
|
||||
#define DP_LINKCTL_ENHANCEDFRAME_ENABLE (1 << 14)
|
||||
#define DP_LINKCTL_SYNCMODE_SHIFT 10
|
||||
#define DP_LINKCTL_SYNCMODE_DISABLE (0 << 10)
|
||||
#define DP_LINKCTL_SYNCMODE_ENABLE (1 << 10)
|
||||
#define DP_LINKCTL_TUSIZE_SHIFT 2
|
||||
#define DP_LINKCTL_TUSIZE_MASK (0x7f << 2)
|
||||
#define DP_LINKCTL_ENABLE_SHIFT 0
|
||||
#define DP_LINKCTL_ENABLE_NO 0
|
||||
#define DP_LINKCTL_ENABLE_YES 1
|
||||
#define DC(i) (0x4e + (i))
|
||||
#define DC_LANE3_DP_LANE3_SHIFT 24
|
||||
#define DC_LANE3_DP_LANE3_MASK (0xff << 24)
|
||||
#define DC_LANE3_DP_LANE3_P0_LEVEL0 (17 << 24)
|
||||
#define DC_LANE3_DP_LANE3_P1_LEVEL0 (21 << 24)
|
||||
#define DC_LANE3_DP_LANE3_P2_LEVEL0 (26 << 24)
|
||||
#define DC_LANE3_DP_LANE3_P3_LEVEL0 (34 << 24)
|
||||
#define DC_LANE3_DP_LANE3_P0_LEVEL1 (26 << 24)
|
||||
#define DC_LANE3_DP_LANE3_P1_LEVEL1 (32 << 24)
|
||||
#define DC_LANE3_DP_LANE3_P2_LEVEL1 (39 << 24)
|
||||
#define DC_LANE3_DP_LANE3_P0_LEVEL2 (34 << 24)
|
||||
#define DC_LANE3_DP_LANE3_P1_LEVEL2 (43 << 24)
|
||||
#define DC_LANE3_DP_LANE3_P0_LEVEL3 (51 << 24)
|
||||
#define DC_LANE2_DP_LANE0_SHIFT 16
|
||||
#define DC_LANE2_DP_LANE0_MASK (0xff << 16)
|
||||
#define DC_LANE2_DP_LANE0_P0_LEVEL0 (17 << 16)
|
||||
#define DC_LANE2_DP_LANE0_P1_LEVEL0 (21 << 16)
|
||||
#define DC_LANE2_DP_LANE0_P2_LEVEL0 (26 << 16)
|
||||
#define DC_LANE2_DP_LANE0_P3_LEVEL0 (34 << 16)
|
||||
#define DC_LANE2_DP_LANE0_P0_LEVEL1 (26 << 16)
|
||||
#define DC_LANE2_DP_LANE0_P1_LEVEL1 (32 << 16)
|
||||
#define DC_LANE2_DP_LANE0_P2_LEVEL1 (39 << 16)
|
||||
#define DC_LANE2_DP_LANE0_P0_LEVEL2 (34 << 16)
|
||||
#define DC_LANE2_DP_LANE0_P1_LEVEL2 (43 << 16)
|
||||
#define DC_LANE2_DP_LANE0_P0_LEVEL3 (51 << 16)
|
||||
#define DC_LANE1_DP_LANE1_SHIFT 8
|
||||
#define DC_LANE1_DP_LANE1_MASK (0xff << 8)
|
||||
#define DC_LANE1_DP_LANE1_P0_LEVEL0 (17 << 8)
|
||||
#define DC_LANE1_DP_LANE1_P1_LEVEL0 (21 << 8)
|
||||
#define DC_LANE1_DP_LANE1_P2_LEVEL0 (26 << 8)
|
||||
#define DC_LANE1_DP_LANE1_P3_LEVEL0 (34 << 8)
|
||||
#define DC_LANE1_DP_LANE1_P0_LEVEL1 (26 << 8)
|
||||
#define DC_LANE1_DP_LANE1_P1_LEVEL1 (32 << 8)
|
||||
#define DC_LANE1_DP_LANE1_P2_LEVEL1 (39 << 8)
|
||||
#define DC_LANE1_DP_LANE1_P0_LEVEL2 (34 << 8)
|
||||
#define DC_LANE1_DP_LANE1_P1_LEVEL2 (43 << 8)
|
||||
#define DC_LANE1_DP_LANE1_P0_LEVEL3 (51 << 8)
|
||||
#define DC_LANE0_DP_LANE2_SHIFT 0
|
||||
#define DC_LANE0_DP_LANE2_MASK 0xff
|
||||
#define DC_LANE0_DP_LANE2_P0_LEVEL0 17
|
||||
#define DC_LANE0_DP_LANE2_P1_LEVEL0 21
|
||||
#define DC_LANE0_DP_LANE2_P2_LEVEL0 26
|
||||
#define DC_LANE0_DP_LANE2_P3_LEVEL0 34
|
||||
#define DC_LANE0_DP_LANE2_P0_LEVEL1 26
|
||||
#define DC_LANE0_DP_LANE2_P1_LEVEL1 32
|
||||
#define DC_LANE0_DP_LANE2_P2_LEVEL1 39
|
||||
#define DC_LANE0_DP_LANE2_P0_LEVEL2 34
|
||||
#define DC_LANE0_DP_LANE2_P1_LEVEL2 43
|
||||
#define DC_LANE0_DP_LANE2_P0_LEVEL3 51
|
||||
#define LANE_DRIVE_CURRENT(i) (0x4e + (i))
|
||||
#define PR(i) (0x52 + (i))
|
||||
#define PR_LANE3_DP_LANE3_SHIFT 24
|
||||
#define PR_LANE3_DP_LANE3_MASK (0xff << 24)
|
||||
#define PR_LANE3_DP_LANE3_D0_LEVEL0 (0 << 24)
|
||||
#define PR_LANE3_DP_LANE3_D1_LEVEL0 (0 << 24)
|
||||
#define PR_LANE3_DP_LANE3_D2_LEVEL0 (0 << 24)
|
||||
#define PR_LANE3_DP_LANE3_D3_LEVEL0 (0 << 24)
|
||||
#define PR_LANE3_DP_LANE3_D0_LEVEL1 (4 << 24)
|
||||
#define PR_LANE3_DP_LANE3_D1_LEVEL1 (6 << 24)
|
||||
#define PR_LANE3_DP_LANE3_D2_LEVEL1 (17 << 24)
|
||||
#define PR_LANE3_DP_LANE3_D0_LEVEL2 (8 << 24)
|
||||
#define PR_LANE3_DP_LANE3_D1_LEVEL2 (13 << 24)
|
||||
#define PR_LANE3_DP_LANE3_D0_LEVEL3 (17 << 24)
|
||||
#define PR_LANE2_DP_LANE0_SHIFT 16
|
||||
#define PR_LANE2_DP_LANE0_MASK (0xff << 16)
|
||||
#define PR_LANE2_DP_LANE0_D0_LEVEL0 (0 << 16)
|
||||
#define PR_LANE2_DP_LANE0_D1_LEVEL0 (0 << 16)
|
||||
#define PR_LANE2_DP_LANE0_D2_LEVEL0 (0 << 16)
|
||||
#define PR_LANE2_DP_LANE0_D3_LEVEL0 (0 << 16)
|
||||
#define PR_LANE2_DP_LANE0_D0_LEVEL1 (4 << 16)
|
||||
#define PR_LANE2_DP_LANE0_D1_LEVEL1 (6 << 16)
|
||||
#define PR_LANE2_DP_LANE0_D2_LEVEL1 (17 << 16)
|
||||
#define PR_LANE2_DP_LANE0_D0_LEVEL2 (8 << 16)
|
||||
#define PR_LANE2_DP_LANE0_D1_LEVEL2 (13 << 16)
|
||||
#define PR_LANE2_DP_LANE0_D0_LEVEL3 (17 << 16)
|
||||
#define PR_LANE1_DP_LANE1_SHIFT 8
|
||||
#define PR_LANE1_DP_LANE1_MASK (0xff >> 8)
|
||||
#define PR_LANE1_DP_LANE1_D0_LEVEL0 (0 >> 8)
|
||||
#define PR_LANE1_DP_LANE1_D1_LEVEL0 (0 >> 8)
|
||||
#define PR_LANE1_DP_LANE1_D2_LEVEL0 (0 >> 8)
|
||||
#define PR_LANE1_DP_LANE1_D3_LEVEL0 (0 >> 8)
|
||||
#define PR_LANE1_DP_LANE1_D0_LEVEL1 (4 >> 8)
|
||||
#define PR_LANE1_DP_LANE1_D1_LEVEL1 (6 >> 8)
|
||||
#define PR_LANE1_DP_LANE1_D2_LEVEL1 (17 >> 8)
|
||||
#define PR_LANE1_DP_LANE1_D0_LEVEL2 (8 >> 8)
|
||||
#define PR_LANE1_DP_LANE1_D1_LEVEL2 (13 >> 8)
|
||||
#define PR_LANE1_DP_LANE1_D0_LEVEL3 (17 >> 8)
|
||||
#define PR_LANE0_DP_LANE2_SHIFT 0
|
||||
#define PR_LANE0_DP_LANE2_MASK 0xff
|
||||
#define PR_LANE0_DP_LANE2_D0_LEVEL0 0
|
||||
#define PR_LANE0_DP_LANE2_D1_LEVEL0 0
|
||||
#define PR_LANE0_DP_LANE2_D2_LEVEL0 0
|
||||
#define PR_LANE0_DP_LANE2_D3_LEVEL0 0
|
||||
#define PR_LANE0_DP_LANE2_D0_LEVEL1 4
|
||||
#define PR_LANE0_DP_LANE2_D1_LEVEL1 6
|
||||
#define PR_LANE0_DP_LANE2_D2_LEVEL1 17
|
||||
#define PR_LANE0_DP_LANE2_D0_LEVEL2 8
|
||||
#define PR_LANE0_DP_LANE2_D1_LEVEL2 13
|
||||
#define PR_LANE0_DP_LANE2_D0_LEVEL3 17
|
||||
#define LANE4_PREEMPHASIS(i) (0x54 + (i))
|
||||
#define POSTCURSOR(i) (0x56 + (i))
|
||||
#define DP_CONFIG(i) (0x58 + (i))
|
||||
#define DP_CONFIG_RD_RESET_VAL_SHIFT 31
|
||||
#define DP_CONFIG_RD_RESET_VAL_POSITIVE (0 << 31)
|
||||
#define DP_CONFIG_RD_RESET_VAL_NEGATIVE (1 << 31)
|
||||
#define DP_CONFIG_IDLE_BEFORE_ATTACH_SHIFT 28
|
||||
#define DP_CONFIG_IDLE_BEFORE_ATTACH_DISABLE (0 << 28)
|
||||
#define DP_CONFIG_IDLE_BEFORE_ATTACH_ENABLE (1 << 28)
|
||||
#define DP_CONFIG_ACTIVESYM_CNTL_SHIFT 26
|
||||
#define DP_CONFIG_ACTIVESYM_CNTL_DISABLE (0 << 26)
|
||||
#define DP_CONFIG_ACTIVESYM_CNTL_ENABLE (1 << 26)
|
||||
#define DP_CONFIG_ACTIVESYM_POLARITY_SHIFT 24
|
||||
#define DP_CONFIG_ACTIVESYM_POLARITY_NEGATIVE (0 << 24)
|
||||
#define DP_CONFIG_ACTIVESYM_POLARITY_POSITIVE (1 << 24)
|
||||
#define DP_CONFIG_ACTIVESYM_FRAC_SHIFT 16
|
||||
#define DP_CONFIG_ACTIVESYM_FRAC_MASK (0xf << 16)
|
||||
#define DP_CONFIG_ACTIVESYM_COUNT_SHIFT 8
|
||||
#define DP_CONFIG_ACTIVESYM_COUNT_MASK (0x7f << 8)
|
||||
#define DP_CONFIG_WATERMARK_SHIFT 0
|
||||
#define DP_CONFIG_WATERMARK_MASK 0x3f
|
||||
#define DP_MN(i) (0x5a + i)
|
||||
#define DP_MN_M_MOD_SHIFT 30
|
||||
#define DP_MN_M_MOD_DEFAULT_MASK (3 << 30)
|
||||
#define DP_MN_M_MOD_NONE (0 << 30)
|
||||
#define DP_MN_M_MOD_INC (1 << 30)
|
||||
#define DP_MN_M_MOD_DEC (2 << 30)
|
||||
#define DP_MN_M_DELTA_SHIFT 24
|
||||
#define DP_MN_M_DELTA_DEFAULT_MASK (0xf << 24)
|
||||
#define DP_MN_N_VAL_SHIFT 0
|
||||
#define DP_MN_N_VAL_DEFAULT_MASK 0xffffff
|
||||
#define DP_PADCTL(i) (0x5c + (i))
|
||||
#define DP_PADCTL_SPARE_SHIFT 25
|
||||
#define DP_PADCTL_SPARE_DEFAULT_MASK (0x7f << 25)
|
||||
#define DP_PADCTL_VCO_2X_SHIFT 24
|
||||
#define DP_PADCTL_VCO_2X_DISABLE (0 << 24)
|
||||
#define DP_PADCTL_VCO_2X_ENABLE (1 << 24)
|
||||
#define DP_PADCTL_PAD_CAL_PD_SHIFT 23
|
||||
#define DP_PADCTL_PAD_CAL_PD_POWERUP (0 << 23)
|
||||
#define DP_PADCTL_PAD_CAL_PD_POWERDOWN (1 << 23)
|
||||
#define DP_PADCTL_TX_PU_SHIFT 22
|
||||
#define DP_PADCTL_TX_PU_DISABLE (0 << 22)
|
||||
#define DP_PADCTL_TX_PU_ENABLE (1 << 22)
|
||||
#define DP_PADCTL_TX_PU_MASK (1 << 22)
|
||||
#define DP_PADCTL_REG_CTRL_SHIFT 20
|
||||
#define DP_PADCTL_REG_CTRL_DEFAULT_MASK (3 << 20)
|
||||
#define DP_PADCTL_VCMMODE_SHIFT 16
|
||||
#define DP_PADCTL_VCMMODE_DEFAULT_MASK (0xf << 16)
|
||||
#define DP_PADCTL_VCMMODE_TRISTATE (0 << 16)
|
||||
#define DP_PADCTL_VCMMODE_TEST_MUX (1 << 16)
|
||||
#define DP_PADCTL_VCMMODE_WEAK_PULLDOWN (2 << 16)
|
||||
#define DP_PADCTL_VCMMODE_STRONG_PULLDOWN (4 << 16)
|
||||
#define DP_PADCTL_TX_PU_VALUE_SHIFT 8
|
||||
#define DP_PADCTL_TX_PU_VALUE_DEFAULT_MASK (0xff << 8)
|
||||
#define DP_PADCTL_COMODE_TXD_3_DP_TXD_3_SHIFT 7
|
||||
#define DP_PADCTL_COMODE_TXD_3_DP_TXD_3_DISABLE (0 << 7)
|
||||
#define DP_PADCTL_COMODE_TXD_3_DP_TXD_3_ENABLE (1 << 7)
|
||||
#define DP_PADCTL_COMODE_TXD_2_DP_TXD_0_SHIFT 6
|
||||
#define DP_PADCTL_COMODE_TXD_2_DP_TXD_0_DISABLE (0 << 6)
|
||||
#define DP_PADCTL_COMODE_TXD_2_DP_TXD_0_ENABLE (1 << 6)
|
||||
#define DP_PADCTL_COMODE_TXD_1_DP_TXD_1_SHIFT 5
|
||||
#define DP_PADCTL_COMODE_TXD_1_DP_TXD_1_DISABLE (0 << 5)
|
||||
#define DP_PADCTL_COMODE_TXD_1_DP_TXD_1_ENABLE (1 << 5)
|
||||
#define DP_PADCTL_COMODE_TXD_0_DP_TXD_2_SHIFT 4
|
||||
#define DP_PADCTL_COMODE_TXD_0_DP_TXD_2_DISABLE (0 << 4)
|
||||
#define DP_PADCTL_COMODE_TXD_0_DP_TXD_2_ENABLE (1 << 4)
|
||||
#define DP_PADCTL_PD_TXD_3_SHIFT 3
|
||||
#define DP_PADCTL_PD_TXD_3_YES (0 << 3)
|
||||
#define DP_PADCTL_PD_TXD_3_NO (1 << 3)
|
||||
#define DP_PADCTL_PD_TXD_0_SHIFT 2
|
||||
#define DP_PADCTL_PD_TXD_0_YES (0 << 2)
|
||||
#define DP_PADCTL_PD_TXD_0_NO (1 << 2)
|
||||
#define DP_PADCTL_PD_TXD_1_SHIFT 1
|
||||
#define DP_PADCTL_PD_TXD_1_YES (0 << 1)
|
||||
#define DP_PADCTL_PD_TXD_1_NO (1 << 1)
|
||||
#define DP_PADCTL_PD_TXD_2_SHIFT 0
|
||||
#define DP_PADCTL_PD_TXD_2_YES 0
|
||||
#define DP_PADCTL_PD_TXD_2_NO 1
|
||||
#define DP_DEBUG(i) (0x5e + i)
|
||||
#define DP_SPARE(i) (0x60 + (i))
|
||||
#define DP_SPARE_REG_SHIFT 3
|
||||
#define DP_SPARE_REG_DEFAULT_MASK (0x1fffffff << 3)
|
||||
#define DP_SPARE_SOR_CLK_SEL_SHIFT 2
|
||||
#define DP_SPARE_SOR_CLK_SEL_DEFAULT_MASK (1 << 2)
|
||||
#define DP_SPARE_SOR_CLK_SEL_SAFE_SORCLK (0 << 2)
|
||||
#define DP_SPARE_SOR_CLK_SEL_MACRO_SORCLK (1 << 2)
|
||||
#define DP_SPARE_PANEL_SHIFT 1
|
||||
#define DP_SPARE_PANEL_EXTERNAL (0 << 1)
|
||||
#define DP_SPARE_PANEL_INTERNAL (1 << 1)
|
||||
#define DP_SPARE_SEQ_ENABLE_SHIFT 0
|
||||
#define DP_SPARE_SEQ_ENABLE_NO 0
|
||||
#define DP_SPARE_SEQ_ENABLE_YES 1
|
||||
#define DP_AUDIO_CTRL 0x62
|
||||
#define DP_AUDIO_HBLANK_SYMBOLS 0x63
|
||||
#define DP_AUDIO_HBLANK_SYMBOLS_MASK 0x1ffff
|
||||
#define DP_AUDIO_HBLANK_SYMBOLS_VALUE_SHIFT 0
|
||||
#define DP_AUDIO_VBLANK_SYMBOLS 0x64
|
||||
#define DP_AUDIO_VBLANK_SYMBOLS_MASK 0x1ffff
|
||||
#define DP_AUDIO_VBLANK_SYMBOLS_SHIFT 0
|
||||
#define DP_GENERIC_INFOFRAME_HEADER 0x65
|
||||
#define DP_GENERIC_INFOFRAME_SUBPACK(i) (0x66 + (i))
|
||||
#define DP_TPG 0x6d
|
||||
#define DP_TPG_LANE3_CHANNELCODING_SHIFT 30
|
||||
#define DP_TPG_LANE3_CHANNELCODING_DISABLE (0 << 30)
|
||||
#define DP_TPG_LANE3_CHANNELCODING_ENABLE (1 << 30)
|
||||
#define DP_TPG_LANE3_SCRAMBLEREN_SHIFT 28
|
||||
#define DP_TPG_LANE3_SCRAMBLEREN_ENABLE_GALIOS (1 << 28)
|
||||
#define DP_TPG_LANE3_SCRAMBLEREN_ENABLE_FIBONACCI (2 << 28)
|
||||
#define DP_TPG_LANE3_PATTERN_SHIFT 24
|
||||
#define DP_TPG_LANE3_PATTERN_DEFAULT_MASK (0xf << 24)
|
||||
#define DP_TPG_LANE3_PATTERN_NOPATTERN (0 << 24)
|
||||
#define DP_TPG_LANE3_PATTERN_TRAINING1 (1 << 24)
|
||||
#define DP_TPG_LANE3_PATTERN_TRAINING2 (2 << 24)
|
||||
#define DP_TPG_LANE3_PATTERN_TRAINING3 (3 << 24)
|
||||
#define DP_TPG_LANE3_PATTERN_D102 (4 << 24)
|
||||
#define DP_TPG_LANE3_PATTERN_SBLERRRATE (5 << 24)
|
||||
#define DP_TPG_LANE3_PATTERN_PRBS7 (6 << 24)
|
||||
#define DP_TPG_LANE3_PATTERN_CSTM (7 << 24)
|
||||
#define DP_TPG_LANE3_PATTERN_HBR2_COMPLIANCE (8 << 24)
|
||||
#define DP_TPG_LANE2_CHANNELCODING_SHIFT 22
|
||||
#define DP_TPG_LANE2_CHANNELCODING_DISABLE (0 << 22)
|
||||
#define DP_TPG_LANE2_CHANNELCODING_ENABLE (1 << 22)
|
||||
#define DP_TPG_LANE2_SCRAMBLEREN_SHIFT 20
|
||||
#define DP_TPG_LANE2_SCRAMBLEREN_DEFAULT_MASK (3 << 20)
|
||||
#define DP_TPG_LANE2_SCRAMBLEREN_DISABLE (0 << 20)
|
||||
#define DP_TPG_LANE2_SCRAMBLEREN_ENABLE_GALIOS (1 << 20)
|
||||
#define DP_TPG_LANE2_SCRAMBLEREN_ENABLE_FIBONACCI (2 << 20)
|
||||
#define DP_TPG_LANE2_PATTERN_SHIFT 16
|
||||
#define DP_TPG_LANE2_PATTERN_DEFAULT_MASK (0xf << 16)
|
||||
#define DP_TPG_LANE2_PATTERN_NOPATTERN (0 << 16)
|
||||
#define DP_TPG_LANE2_PATTERN_TRAINING1 (1 << 16)
|
||||
#define DP_TPG_LANE2_PATTERN_TRAINING2 (2 << 16)
|
||||
#define DP_TPG_LANE2_PATTERN_TRAINING3 (3 << 16)
|
||||
#define DP_TPG_LANE2_PATTERN_D102 (4 << 16)
|
||||
#define DP_TPG_LANE2_PATTERN_SBLERRRATE (5 << 16)
|
||||
#define DP_TPG_LANE2_PATTERN_PRBS7 (6 << 16)
|
||||
#define DP_TPG_LANE2_PATTERN_CSTM (7 << 16)
|
||||
#define DP_TPG_LANE2_PATTERN_HBR2_COMPLIANCE (8 << 16)
|
||||
#define DP_TPG_LANE1_CHANNELCODING_SHIFT 14
|
||||
#define DP_TPG_LANE1_CHANNELCODING_DISABLE (0 << 14)
|
||||
#define DP_TPG_LANE1_CHANNELCODING_ENABLE (1 << 14)
|
||||
#define DP_TPG_LANE1_SCRAMBLEREN_SHIFT 12
|
||||
#define DP_TPG_LANE1_SCRAMBLEREN_DEFAULT_MASK (3 << 12)
|
||||
#define DP_TPG_LANE1_SCRAMBLEREN_DISABLE (0 << 12)
|
||||
#define DP_TPG_LANE1_SCRAMBLEREN_ENABLE_GALIOS (1 << 12)
|
||||
#define DP_TPG_LANE1_SCRAMBLEREN_ENABLE_FIBONACCI (2 << 12)
|
||||
#define DP_TPG_LANE1_PATTERN_SHIFT 8
|
||||
#define DP_TPG_LANE1_PATTERN_DEFAULT_MASK (0xf << 8)
|
||||
#define DP_TPG_LANE1_PATTERN_NOPATTERN (0 << 8)
|
||||
#define DP_TPG_LANE1_PATTERN_TRAINING1 (1 << 8)
|
||||
#define DP_TPG_LANE1_PATTERN_TRAINING2 (2 << 8)
|
||||
#define DP_TPG_LANE1_PATTERN_TRAINING3 (3 << 8)
|
||||
#define DP_TPG_LANE1_PATTERN_D102 (4 << 8)
|
||||
#define DP_TPG_LANE1_PATTERN_SBLERRRATE (5 << 8)
|
||||
#define DP_TPG_LANE1_PATTERN_PRBS7 (6 << 8)
|
||||
#define DP_TPG_LANE1_PATTERN_CSTM (7 << 8)
|
||||
#define DP_TPG_LANE1_PATTERN_HBR2_COMPLIANCE (8 << 8)
|
||||
#define DP_TPG_LANE0_CHANNELCODING_SHIFT 6
|
||||
#define DP_TPG_LANE0_CHANNELCODING_DISABLE (0 << 6)
|
||||
#define DP_TPG_LANE0_CHANNELCODING_ENABLE (1 << 6)
|
||||
#define DP_TPG_LANE0_SCRAMBLEREN_SHIFT 4
|
||||
#define DP_TPG_LANE0_SCRAMBLEREN_DEFAULT_MASK (3 << 4)
|
||||
#define DP_TPG_LANE0_SCRAMBLEREN_DISABLE (0 << 4)
|
||||
#define DP_TPG_LANE0_SCRAMBLEREN_ENABLE_GALIOS (1 << 4)
|
||||
#define DP_TPG_LANE0_SCRAMBLEREN_ENABLE_FIBONACCI (2 << 4)
|
||||
#define DP_TPG_LANE0_PATTERN_SHIFT 0
|
||||
#define DP_TPG_LANE0_PATTERN_DEFAULT_MASK 0xf
|
||||
#define DP_TPG_LANE0_PATTERN_NOPATTERN 0
|
||||
#define DP_TPG_LANE0_PATTERN_TRAINING1 1
|
||||
#define DP_TPG_LANE0_PATTERN_TRAINING2 2
|
||||
#define DP_TPG_LANE0_PATTERN_TRAINING3 3
|
||||
#define DP_TPG_LANE0_PATTERN_D102 4
|
||||
#define DP_TPG_LANE0_PATTERN_SBLERRRATE 5
|
||||
#define DP_TPG_LANE0_PATTERN_PRBS7 6
|
||||
#define DP_TPG_LANE0_PATTERN_CSTM 7
|
||||
#define DP_TPG_LANE0_PATTERN_HBR2_COMPLIANCE 8
|
||||
|
||||
enum {
|
||||
training_pattern_disabled = 0,
|
||||
training_pattern_1 = 1,
|
||||
training_pattern_2 = 2,
|
||||
training_pattern_3 = 3,
|
||||
training_pattern_none = 0xff
|
||||
};
|
||||
|
||||
enum tegra_dc_sor_protocol {
|
||||
SOR_DP,
|
||||
SOR_LVDS,
|
||||
};
|
||||
|
||||
#define SOR_LINK_SPEED_G1_62 6
|
||||
#define SOR_LINK_SPEED_G2_7 10
|
||||
#define SOR_LINK_SPEED_G5_4 20
|
||||
#define SOR_LINK_SPEED_LVDS 7
|
||||
|
||||
struct tegra_dp_link_config {
|
||||
int is_valid;
|
||||
|
||||
/* Supported configuration */
|
||||
u8 max_link_bw;
|
||||
u8 max_lane_count;
|
||||
int downspread;
|
||||
int support_enhanced_framing;
|
||||
u32 bits_per_pixel;
|
||||
int alt_scramber_reset_cap; /* true for eDP */
|
||||
int only_enhanced_framing; /* enhanced_frame_en ignored */
|
||||
|
||||
/* Actual configuration */
|
||||
u8 link_bw;
|
||||
u8 lane_count;
|
||||
int enhanced_framing;
|
||||
int scramble_ena;
|
||||
|
||||
u32 activepolarity;
|
||||
u32 active_count;
|
||||
u32 tu_size;
|
||||
u32 active_frac;
|
||||
u32 watermark;
|
||||
|
||||
s32 hblank_sym;
|
||||
s32 vblank_sym;
|
||||
|
||||
/* Training data */
|
||||
u32 drive_current;
|
||||
u32 preemphasis;
|
||||
u32 postcursor;
|
||||
};
|
||||
|
||||
struct tegra_dc_sor_data {
|
||||
void *base;
|
||||
void *pmc_base;
|
||||
u8 portnum; /* 0 or 1 */
|
||||
int power_is_up;
|
||||
};
|
||||
|
||||
#define TEGRA_SOR_TIMEOUT_MS 1000
|
||||
#define TEGRA_SOR_ATTACH_TIMEOUT_MS 1000
|
||||
|
||||
int tegra_dc_sor_enable_dp(struct tegra_dc_sor_data *sor,
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const struct tegra_dp_link_config *link_cfg);
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||||
int tegra_dc_sor_set_power_state(struct tegra_dc_sor_data *sor, int pu_pd);
|
||||
void tegra_dc_sor_set_dp_linkctl(struct tegra_dc_sor_data *sor, int ena,
|
||||
u8 training_pattern, const struct tegra_dp_link_config *link_cfg);
|
||||
void tegra_dc_sor_set_link_bandwidth(struct tegra_dc_sor_data *sor, u8 link_bw);
|
||||
void tegra_dc_sor_set_lane_count(struct tegra_dc_sor_data *sor, u8 lane_count);
|
||||
void tegra_dc_sor_set_panel_power(struct tegra_dc_sor_data *sor,
|
||||
int power_up);
|
||||
void tegra_dc_sor_set_internal_panel(struct tegra_dc_sor_data *sor, int is_int);
|
||||
void tegra_dc_sor_read_link_config(struct tegra_dc_sor_data *sor, u8 *link_bw,
|
||||
u8 *lane_count);
|
||||
void tegra_dc_sor_set_lane_parm(struct tegra_dc_sor_data *sor,
|
||||
const struct tegra_dp_link_config *link_cfg);
|
||||
void tegra_dc_sor_power_down_unused_lanes(struct tegra_dc_sor_data *sor,
|
||||
const struct tegra_dp_link_config *link_cfg);
|
||||
|
||||
int tegra_dc_sor_attach(struct tegra_dc_sor_data *sor,
|
||||
const struct tegra_dp_link_config *link_cfg,
|
||||
const struct display_timing *timing);
|
||||
int tegra_dc_sor_init(struct tegra_dc_sor_data **sorp);
|
||||
#endif
|
||||
|
|
@ -130,6 +130,9 @@ enum fdt_compat_id {
|
|||
COMPAT_NVIDIA_TEGRA20_KBC, /* Tegra20 Keyboard */
|
||||
COMPAT_NVIDIA_TEGRA20_NAND, /* Tegra2 NAND controller */
|
||||
COMPAT_NVIDIA_TEGRA20_PWM, /* Tegra 2 PWM controller */
|
||||
COMPAT_NVIDIA_TEGRA124_DC, /* Tegra 124 Display controller */
|
||||
COMPAT_NVIDIA_TEGRA124_SOR, /* Tegra 124 Serial Output Resource */
|
||||
COMPAT_NVIDIA_TEGRA124_PMC, /* Tegra 124 power mgmt controller */
|
||||
COMPAT_NVIDIA_TEGRA20_DC, /* Tegra 2 Display controller */
|
||||
COMPAT_NVIDIA_TEGRA124_SDMMC, /* Tegra124 SDMMC controller */
|
||||
COMPAT_NVIDIA_TEGRA30_SDMMC, /* Tegra30 SDMMC controller */
|
||||
|
|
|
|||
|
|
@ -30,6 +30,9 @@ static const char * const compat_names[COMPAT_COUNT] = {
|
|||
COMPAT(NVIDIA_TEGRA20_KBC, "nvidia,tegra20-kbc"),
|
||||
COMPAT(NVIDIA_TEGRA20_NAND, "nvidia,tegra20-nand"),
|
||||
COMPAT(NVIDIA_TEGRA20_PWM, "nvidia,tegra20-pwm"),
|
||||
COMPAT(NVIDIA_TEGRA124_DC, "nvidia,tegra124-dc"),
|
||||
COMPAT(NVIDIA_TEGRA124_SOR, "nvidia,tegra124-sor"),
|
||||
COMPAT(NVIDIA_TEGRA124_PMC, "nvidia,tegra124-pmc"),
|
||||
COMPAT(NVIDIA_TEGRA20_DC, "nvidia,tegra20-dc"),
|
||||
COMPAT(NVIDIA_TEGRA124_SDMMC, "nvidia,tegra124-sdhci"),
|
||||
COMPAT(NVIDIA_TEGRA30_SDMMC, "nvidia,tegra30-sdhci"),
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue