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Revert "ppc/85xx/pci: fsl_pci_init: pcie agent mode support"

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This reverts commit 70ed869ea5.

There isn't any need to modify the API for fsl_pci_init_port to pass the
status of host/agent(end-point) status.  We can determine that
internally to fsl_pci_init_port.  Revert the patch that makes the API
change.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Kumar Gala 2009-11-04 01:29:04 -06:00
parent ff88229549
commit 01471d538f
6 changed files with 13 additions and 28 deletions
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6
board/freescale/mpc8572ds/mpc8572ds.c
View file

@ -199,7 +199,7 @@ void pci_init_board(void)
pcie_ep ? "End Point" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
&pcie3_hose, first_free_busno, pcie_ep);
&pcie3_hose, first_free_busno);
/*
* Activate ULI1575 legacy chip by performing a fake
* memory access. Needed to make ULI RTC work.
@ -231,7 +231,7 @@ void pci_init_board(void)
pcie_ep ? "End Point" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
&pcie2_hose, first_free_busno, pcie_ep);
&pcie2_hose, first_free_busno);
} else {
printf (" PCIE2: disabled\n");
}
@ -251,7 +251,7 @@ void pci_init_board(void)
pcie_ep ? "End Point" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
&pcie1_hose, first_free_busno, pcie_ep);
&pcie1_hose, first_free_busno);
} else {
printf (" PCIE1: disabled\n");
}

4
board/freescale/p1_p2_rdb/pci.c
View file

@ -71,7 +71,7 @@ void pci_init_board(void)
pcie_ep ? "End Point" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
&pcie2_hose, first_free_busno, pcie_ep);
&pcie2_hose, first_free_busno);
} else {
printf (" PCIE2: disabled\n");
}
@ -90,7 +90,7 @@ void pci_init_board(void)
pcie_ep ? "End Point" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
&pcie1_hose, first_free_busno, pcie_ep);
&pcie1_hose, first_free_busno);
} else {
printf (" PCIE1: disabled\n");
}

6
board/freescale/p2020ds/p2020ds.c
View file

@ -227,7 +227,7 @@ void pci_init_board(void)
pcie_ep ? "End Point" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
&pcie2_hose, first_free_busno, pcie_ep);
&pcie2_hose, first_free_busno);
/*
* The workaround doesn't work on p2020 because the location
@ -267,7 +267,7 @@ void pci_init_board(void)
pcie_ep ? "End Point" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
&pcie3_hose, first_free_busno, pcie_ep);
&pcie3_hose, first_free_busno);
} else {
printf(" PCIE3: disabled\n");
}
@ -286,7 +286,7 @@ void pci_init_board(void)
pcie_ep ? "End Point" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
&pcie1_hose, first_free_busno, pcie_ep);
&pcie1_hose, first_free_busno);
} else {
printf(" PCIE1: disabled\n");
}

4
board/sbc8548/sbc8548.c
View file

@ -359,7 +359,7 @@ pci_init_board(void)
SET_STD_PCI_INFO(pci_info[num], 1);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
&pci1_hose, first_free_busno, 0);
&pci1_hose, first_free_busno);
} else {
printf (" PCI: disabled\n");
}
@ -378,7 +378,7 @@ pci_init_board(void)
SET_STD_PCIE_INFO(pci_info[num], 1);
printf (" PCIE at base address %lx\n", pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
&pcie1_hose, first_free_busno, 0);
&pcie1_hose, first_free_busno);
} else {
printf (" PCIE: disabled\n");
}

18
drivers/pci/fsl_pci_init.c
View file

@ -1,5 +1,5 @@
/*
* Copyright 2007-2009 Freescale Semiconductor, Inc.
* Copyright 2007 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
@ -413,27 +413,13 @@ void fsl_pci_init(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data)
}
int fsl_pci_init_port(struct fsl_pci_info *pci_info,
struct pci_controller *hose, int busno, int pcie_ep)
struct pci_controller *hose, int busno)
{
volatile ccsr_fsl_pci_t *pci;
struct pci_region *r;
pci = (ccsr_fsl_pci_t *) pci_info->regs;
if (pcie_ep) {
volatile pit_t *pi = &pci->pit[2];
pci_setup_indirect(hose, (u32)&pci->cfg_addr,
(u32)&pci->cfg_data);
out_be32(&pi->pitar, 0);
out_be32(&pi->piwbar, 0);
out_be32(&pi->piwar, PIWAR_EN | PIWAR_LOCAL |
PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP | PIWAR_IWS_4K);
fsl_pci_config_unlock(hose);
return 0;
}
/* on non-PCIe controllers we don't have pme_msg_det so this code
* should do nothing since the read will return 0
*/

3
include/asm-ppc/fsl_pci.h
View file

@ -62,7 +62,6 @@ typedef struct pci_inbound_window {
#define PIWAR_LOCAL 0x00f00000
#define PIWAR_READ_SNOOP 0x00050000
#define PIWAR_WRITE_SNOOP 0x00005000
#define PIWAR_IWS_4K 0x0000000b
u32 res2[3];
} pit_t;
@ -172,7 +171,7 @@ struct fsl_pci_info {
};
int fsl_pci_init_port(struct fsl_pci_info *pci_info,
struct pci_controller *hose, int busno, int pcie_ep);
struct pci_controller *hose, int busno);
#define SET_STD_PCI_INFO(x, num) \
{ \