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8xxx: Break out DMA code to a common file
DMA support is now enabled via the CONFIG_FSL_DMA define instead of the previous CONFIG_DDR_ECC Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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parent
29c3518246
commit
017f11f68e
7 changed files with 102 additions and 102 deletions
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@ -264,53 +264,6 @@ reset_85xx_watchdog(void)
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}
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#endif /* CONFIG_WATCHDOG */
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#if defined(CONFIG_DDR_ECC)
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void dma_init(void) {
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volatile ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR);
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volatile fsl_dma_t *dma = &dma_base->dma[0];
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dma->satr = 0x00040000;
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dma->datr = 0x00040000;
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dma->sr = 0xffffffff; /* clear any errors */
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asm("sync; isync; msync");
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return;
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}
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uint dma_check(void) {
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volatile ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR);
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volatile fsl_dma_t *dma = &dma_base->dma[0];
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volatile uint status = dma->sr;
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/* While the channel is busy, spin */
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while((status & 4) == 4) {
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status = dma->sr;
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}
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/* clear MR[CS] channel start bit */
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dma->mr &= 0x00000001;
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asm("sync;isync;msync");
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if (status != 0) {
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printf ("DMA Error: status = %x\n", status);
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}
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return status;
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}
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int dma_xfer(void *dest, uint count, void *src) {
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volatile ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR);
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volatile fsl_dma_t *dma = &dma_base->dma[0];
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dma->dar = (uint) dest;
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dma->sar = (uint) src;
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dma->bcr = count;
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dma->mr = 0xf000004;
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asm("sync;isync;msync");
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dma->mr = 0xf000005;
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asm("sync;isync;msync");
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return dma_check();
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}
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#endif
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/*
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* Configures a UPM. The function requires the respective MxMR to be set
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* before calling this function. "size" is the number or entries, not a sizeof.
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@ -186,61 +186,6 @@ watchdog_reset(void)
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}
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#endif /* CONFIG_WATCHDOG */
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#if defined(CONFIG_DDR_ECC)
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void
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dma_init(void)
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{
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volatile ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC86xx_DMA_ADDR);
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volatile fsl_dma_t *dma = &dma_base->dma[0];
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dma->satr = 0x00040000;
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dma->datr = 0x00040000;
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dma->sr = 0xffffffff; /* clear any errors */
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asm("sync; isync");
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}
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uint
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dma_check(void)
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{
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volatile ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC86xx_DMA_ADDR);
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volatile fsl_dma_t *dma = &dma_base->dma[0];
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volatile uint status = dma->sr;
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/* While the channel is busy, spin */
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while ((status & 4) == 4) {
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status = dma->sr;
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}
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/* clear MR[CS] channel start bit */
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dma->mr &= 0x00000001;
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asm("sync;isync");
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if (status != 0) {
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printf("DMA Error: status = %x\n", status);
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}
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return status;
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}
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int
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dma_xfer(void *dest, uint count, void *src)
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{
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volatile ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC86xx_DMA_ADDR);
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volatile fsl_dma_t *dma = &dma_base->dma[0];
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dma->dar = (uint) dest;
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dma->sar = (uint) src;
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dma->bcr = count;
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dma->mr = 0xf000004;
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asm("sync;isync");
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dma->mr = 0xf000005;
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asm("sync;isync");
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return dma_check();
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}
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#endif /* CONFIG_DDR_ECC */
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/*
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* Print out the state of various machine registers.
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* Currently prints out LAWs, BR0/OR0, and BATs
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@ -26,6 +26,7 @@ include $(TOPDIR)/config.mk
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LIB := $(obj)libdma.a
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COBJS-$(CONFIG_FSLDMAFEC) += MCD_tasksInit.o MCD_dmaApi.o MCD_tasks.o
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COBJS-$(CONFIG_FSL_DMA) += fsl_dma.o
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COBJS := $(COBJS-y)
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SRCS := $(COBJS:.o=.c)
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92
drivers/dma/fsl_dma.c
Normal file
92
drivers/dma/fsl_dma.c
Normal file
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@ -0,0 +1,92 @@
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/*
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* Copyright 2004,2007,2008 Freescale Semiconductor, Inc.
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* (C) Copyright 2002, 2003 Motorola Inc.
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* Xianghua Xiao (X.Xiao@motorola.com)
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*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <common.h>
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#include <asm/fsl_dma.h>
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#if defined(CONFIG_MPC85xx)
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volatile ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR);
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#elif defined(CONFIG_MPC86xx)
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volatile ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC86xx_DMA_ADDR);
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#else
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#error "Freescale DMA engine not supported on your processor"
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#endif
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static void dma_sync(void)
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{
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#if defined(CONFIG_MPC85xx)
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asm("sync; isync; msync");
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#elif defined(CONFIG_MPC86xx)
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asm("sync; isync");
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#endif
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}
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static uint dma_check(void) {
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volatile fsl_dma_t *dma = &dma_base->dma[0];
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volatile uint status = dma->sr;
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/* While the channel is busy, spin */
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while (status & 4)
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status = dma->sr;
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/* clear MR[CS] channel start bit */
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dma->mr &= 1;
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dma_sync();
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if (status != 0)
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printf ("DMA Error: status = %x\n", status);
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return status;
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}
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void dma_init(void) {
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volatile fsl_dma_t *dma = &dma_base->dma[0];
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dma->satr = 0x00040000;
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dma->datr = 0x00040000;
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dma->sr = 0xffffffff; /* clear any errors */
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dma_sync();
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}
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int dma_xfer(void *dest, uint count, void *src) {
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volatile fsl_dma_t *dma = &dma_base->dma[0];
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dma->dar = (uint) dest;
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dma->sar = (uint) src;
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dma->bcr = count;
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/* Disable bandwidth control, use direct transfer mode */
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dma->mr = 0xf000004;
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dma_sync();
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/* Start the transfer */
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dma->mr = 0xf000005;
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dma_sync();
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return dma_check();
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}
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@ -29,4 +29,11 @@
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#endif
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#endif
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#ifndef CONFIG_FSL_DMA
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#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) && \
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(defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx))
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#define CONFIG_FSL_DMA
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#endif
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#endif
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#endif /* _ASM_CONFIG_H_ */
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@ -96,6 +96,7 @@
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#undef CONFIG_DDR_SPD
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#define CONFIG_DDR_DLL /* possible DLL fix needed */
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#define CONFIG_DDR_ECC /* only for ECC DDR module */
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#define CONFIG_FSL_DMA /* use DMA to init DDR ECC */
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#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
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@ -98,6 +98,7 @@
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#undef CONFIG_DDR_SPD
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#define CONFIG_DDR_DLL /* possible DLL fix needed */
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#define CONFIG_DDR_ECC /* only for ECC DDR module */
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#define CONFIG_FSL_DMA /* use DMA to init DDR ECC */
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#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
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