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drivers/pci/layerscape: Add EP mode support
The patch will initialize PCIe controller on EP mode 1. Setup bar: bar0 32bit 4K for specific configuration bar1 32bit 8K for MSIX bar2 64bit 4K for descriptor of memory bar4 64bit 1M for DMA memory test 2. Setup iATU: iATU inbound 0-3 to map bar transaction to memory address started at CONFIG_SYS_PCI_EP_MEMORY_BASE iATU outbound 0 to map 4G memory space Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
This commit is contained in:
Minghuan Lian
York Sun
parent
ed5b580b38
commit
01cafcedbf
1 changed files with 135 additions and 2 deletions
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@ -25,6 +25,10 @@
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#define CONFIG_SYS_PCI_MEMORY_SIZE (2 * 1024 * 1024 * 1024UL) /* 2G */
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#endif
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#ifndef CONFIG_SYS_PCI_EP_MEMORY_BASE
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#define CONFIG_SYS_PCI_EP_MEMORY_BASE CONFIG_SYS_LOAD_ADDR
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#endif
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/* iATU registers */
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#define PCIE_ATU_VIEWPORT 0x900
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#define PCIE_ATU_REGION_INBOUND (0x1 << 31)
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@ -41,6 +45,7 @@
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#define PCIE_ATU_CR2 0x908
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#define PCIE_ATU_ENABLE (0x1 << 31)
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#define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30)
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#define PCIE_ATU_BAR_NUM(bar) ((bar) << 8)
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#define PCIE_ATU_LOWER_BASE 0x90C
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#define PCIE_ATU_UPPER_BASE 0x910
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#define PCIE_ATU_LIMIT 0x914
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@ -52,6 +57,7 @@
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/* LUT registers */
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#define PCIE_LUT_BASE 0x80000
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#define PCIE_LUT_LCTRL0 0x7F8
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#define PCIE_LUT_DBG 0x7FC
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#define PCIE_DBI_RO_WR_EN 0x8bc
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@ -65,6 +71,25 @@
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#define PCIE_DBI_SIZE 0x100000 /* 1M */
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#define PCIE_LCTRL0_CFG2_ENABLE (1 << 31)
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#define PCIE_LCTRL0_VF(vf) ((vf) << 22)
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#define PCIE_LCTRL0_PF(pf) ((pf) << 16)
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#define PCIE_LCTRL0_VF_ACTIVE (1 << 21)
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#define PCIE_LCTRL0_VAL(pf, vf) (PCIE_LCTRL0_PF(pf) | \
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PCIE_LCTRL0_VF(vf) | \
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((vf) == 0 ? 0 : PCIE_LCTRL0_VF_ACTIVE) | \
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PCIE_LCTRL0_CFG2_ENABLE)
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#define PCIE_NO_SRIOV_BAR_BASE 0x1000
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#define PCIE_PF_NUM 2
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#define PCIE_VF_NUM 64
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#define PCIE_BAR0_SIZE (4 * 1024) /* 4K */
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#define PCIE_BAR1_SIZE (8 * 1024) /* 8K for MSIX */
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#define PCIE_BAR2_SIZE (4 * 1024) /* 4K */
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#define PCIE_BAR4_SIZE (1 * 1024 * 1024) /* 1M */
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struct ls_pcie {
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int idx;
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void __iomem *dbi;
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@ -76,6 +101,7 @@ struct ls_pcie {
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struct ls_pcie_info {
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unsigned long regs;
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int pci_num;
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u64 phys_base;
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u64 cfg0_phys;
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u64 cfg0_size;
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u64 cfg1_phys;
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@ -91,6 +117,7 @@ struct ls_pcie_info {
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#define SET_LS_PCIE_INFO(x, num) \
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{ \
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x.regs = CONFIG_SYS_PCIE##num##_ADDR; \
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x.phys_base = CONFIG_SYS_PCIE##num##_PHYS_ADDR; \
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x.cfg0_phys = CONFIG_SYS_PCIE_CFG0_PHYS_OFF + \
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CONFIG_SYS_PCIE##num##_PHYS_ADDR; \
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x.cfg0_size = CONFIG_SYS_PCIE_CFG0_SIZE; \
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@ -197,6 +224,18 @@ static void ls_pcie_iatu_outbound_set(struct ls_pcie *pcie, int idx, int type,
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writel(PCIE_ATU_ENABLE, pcie->dbi + PCIE_ATU_CR2);
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}
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/* Use bar match mode and MEM type as default */
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static void ls_pcie_iatu_inbound_set(struct ls_pcie *pcie, int idx,
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int bar, u64 phys)
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{
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writel(PCIE_ATU_REGION_INBOUND | idx, pcie->dbi + PCIE_ATU_VIEWPORT);
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writel((u32)phys, pcie->dbi + PCIE_ATU_LOWER_TARGET);
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writel(phys >> 32, pcie->dbi + PCIE_ATU_UPPER_TARGET);
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writel(PCIE_ATU_TYPE_MEM, pcie->dbi + PCIE_ATU_CR1);
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writel(PCIE_ATU_ENABLE | PCIE_ATU_BAR_MODE_ENABLE |
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PCIE_ATU_BAR_NUM(bar), pcie->dbi + PCIE_ATU_CR2);
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}
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static void ls_pcie_setup_atu(struct ls_pcie *pcie, struct ls_pcie_info *info)
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{
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#ifdef DEBUG
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@ -350,6 +389,97 @@ static void ls_pcie_setup_ctrl(struct ls_pcie *pcie,
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#endif
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}
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static void ls_pcie_ep_setup_atu(struct ls_pcie *pcie,
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struct ls_pcie_info *info)
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{
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u64 phys = CONFIG_SYS_PCI_EP_MEMORY_BASE;
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/* ATU 0 : INBOUND : map BAR0 */
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ls_pcie_iatu_inbound_set(pcie, PCIE_ATU_REGION_INDEX0, 0, phys);
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/* ATU 1 : INBOUND : map BAR1 */
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phys += PCIE_BAR1_SIZE;
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ls_pcie_iatu_inbound_set(pcie, PCIE_ATU_REGION_INDEX1, 1, phys);
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/* ATU 2 : INBOUND : map BAR2 */
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phys += PCIE_BAR2_SIZE;
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ls_pcie_iatu_inbound_set(pcie, PCIE_ATU_REGION_INDEX2, 2, phys);
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/* ATU 3 : INBOUND : map BAR4 */
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phys = CONFIG_SYS_PCI_EP_MEMORY_BASE + PCIE_BAR4_SIZE;
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ls_pcie_iatu_inbound_set(pcie, PCIE_ATU_REGION_INDEX3, 4, phys);
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/* ATU 0 : OUTBOUND : map 4G MEM */
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ls_pcie_iatu_outbound_set(pcie, PCIE_ATU_REGION_INDEX0,
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PCIE_ATU_TYPE_MEM,
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info->phys_base,
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0,
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4 * 1024 * 1024 * 1024ULL);
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}
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/* BAR0 and BAR1 are 32bit BAR2 and BAR4 are 64bit */
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static void ls_pcie_ep_setup_bar(void *bar_base, int bar, u32 size)
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{
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if (size < 4 * 1024)
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return;
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switch (bar) {
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case 0:
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writel(size - 1, bar_base + PCI_BASE_ADDRESS_0);
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break;
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case 1:
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writel(size - 1, bar_base + PCI_BASE_ADDRESS_1);
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break;
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case 2:
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writel(size - 1, bar_base + PCI_BASE_ADDRESS_2);
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writel(0, bar_base + PCI_BASE_ADDRESS_3);
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break;
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case 4:
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writel(size - 1, bar_base + PCI_BASE_ADDRESS_4);
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writel(0, bar_base + PCI_BASE_ADDRESS_5);
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break;
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default:
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break;
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}
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}
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static void ls_pcie_ep_setup_bars(void *bar_base)
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{
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/* BAR0 - 32bit - 4K configuration */
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ls_pcie_ep_setup_bar(bar_base, 0, PCIE_BAR0_SIZE);
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/* BAR1 - 32bit - 8K MSIX*/
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ls_pcie_ep_setup_bar(bar_base, 1, PCIE_BAR1_SIZE);
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/* BAR2 - 64bit - 4K MEM desciptor */
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ls_pcie_ep_setup_bar(bar_base, 2, PCIE_BAR2_SIZE);
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/* BAR4 - 64bit - 1M MEM*/
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ls_pcie_ep_setup_bar(bar_base, 4, PCIE_BAR4_SIZE);
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}
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static void ls_pcie_setup_ep(struct ls_pcie *pcie, struct ls_pcie_info *info)
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{
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struct pci_controller *hose = &pcie->hose;
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pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0);
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int sriov;
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sriov = pci_hose_find_ext_capability(hose, dev, PCI_EXT_CAP_ID_SRIOV);
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if (sriov) {
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int pf, vf;
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for (pf = 0; pf < PCIE_PF_NUM; pf++) {
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for (vf = 0; vf <= PCIE_VF_NUM; vf++) {
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writel(PCIE_LCTRL0_VAL(pf, vf),
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pcie->dbi + PCIE_LUT_BASE +
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PCIE_LUT_LCTRL0);
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ls_pcie_ep_setup_bars(pcie->dbi);
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ls_pcie_ep_setup_atu(pcie, info);
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}
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}
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/* Disable CFG2 */
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writel(0, pcie->dbi + PCIE_LUT_BASE + PCIE_LUT_LCTRL0);
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} else {
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ls_pcie_ep_setup_bars(pcie->dbi + PCIE_NO_SRIOV_BAR_BASE);
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ls_pcie_ep_setup_atu(pcie, info);
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}
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}
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int ls_pcie_init_ctrl(int busno, enum srds_prtcl dev, struct ls_pcie_info *info)
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{
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struct ls_pcie *pcie;
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@ -426,6 +556,11 @@ int ls_pcie_init_ctrl(int busno, enum srds_prtcl dev, struct ls_pcie_info *info)
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printf("PCIe%u: %s ", info->pci_num,
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ep_mode ? "Endpoint" : "Root Complex");
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if (ep_mode)
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ls_pcie_setup_ep(pcie, info);
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else
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ls_pcie_setup_ctrl(pcie, info);
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linkup = ls_pcie_link_up(pcie);
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if (!linkup) {
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@ -443,8 +578,6 @@ int ls_pcie_init_ctrl(int busno, enum srds_prtcl dev, struct ls_pcie_info *info)
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if (ep_mode)
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return busno;
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ls_pcie_setup_ctrl(pcie, info);
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pci_register_hose(hose);
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hose->last_busno = pci_hose_scan(hose);
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