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riscv: sifive: fu540: add SPL configuration
Add a support for SPL which will boot from L2 LIM (0x0800_0000) and then SPL will boot U-Boot FIT image (OpenSBI FW_DYNAMIC + u-boot.bin) from MMC boot devices. SPL related code is leveraged from FSBL (https://github.com/sifive/freedom-u540-c000-bootloader.git) Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
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9 changed files with 172 additions and 1 deletions
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@ -3,5 +3,9 @@
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# Copyright (C) 2020 SiFive, Inc
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# Pragnesh Patel <pragnesh.patel@sifive.com>
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ifeq ($(CONFIG_SPL_BUILD),y)
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obj-y += spl.o
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else
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obj-y += dram.o
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obj-y += cpu.o
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endif
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23
arch/riscv/cpu/fu540/spl.c
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23
arch/riscv/cpu/fu540/spl.c
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@ -0,0 +1,23 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2020 SiFive, Inc
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* Pragnesh Patel <pragnesh.patel@sifive.com>
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*/
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#include <dm.h>
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#include <log.h>
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int soc_spl_init(void)
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{
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int ret;
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struct udevice *dev;
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/* DDR init */
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ret = uclass_get_device(UCLASS_RAM, 0, &dev);
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if (ret) {
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debug("DRAM init failed: %d\n", ret);
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return ret;
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}
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return 0;
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}
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@ -4,6 +4,7 @@
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*/
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#include "fu540-c000-u-boot.dtsi"
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#include "fu540-hifive-unleashed-a00-ddr.dtsi"
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/ {
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aliases {
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@ -26,3 +27,7 @@
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u-boot,dm-spl;
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};
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};
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&gpio {
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u-boot,dm-spl;
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};
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14
arch/riscv/include/asm/arch-fu540/spl.h
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14
arch/riscv/include/asm/arch-fu540/spl.h
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@ -0,0 +1,14 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2020 SiFive, Inc.
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*
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* Authors:
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* Pragnesh Patel <pragnesh.patel@sifve.com>
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*/
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#ifndef _SPL_SIFIVE_H
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#define _SPL_SIFIVE_H
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int soc_spl_init(void);
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#endif /* _SPL_SIFIVE_H */
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@ -13,12 +13,20 @@ config SYS_CONFIG_NAME
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default "sifive-fu540"
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config SYS_TEXT_BASE
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default 0x80200000 if SPL
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default 0x80000000 if !RISCV_SMODE
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default 0x80200000 if RISCV_SMODE
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config SPL_TEXT_BASE
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default 0x08000000
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config SPL_OPENSBI_LOAD_ADDR
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default 0x80000000
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config BOARD_SPECIFIC_OPTIONS # dummy
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def_bool y
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select GENERIC_RISCV
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select SIFIVE_FU540
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select SUPPORT_SPL
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select RAM
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select SPL_RAM if SPL
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imply CMD_DHCP
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@ -3,3 +3,7 @@
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# Copyright (c) 2019 Western Digital Corporation or its affiliates.
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obj-y += fu540.o
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ifdef CONFIG_SPL_BUILD
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obj-y += spl.o
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endif
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@ -14,6 +14,7 @@
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <misc.h>
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#include <spl.h>
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/*
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* This define is a value used for error/unknown serial.
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@ -117,3 +118,23 @@ int board_init(void)
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return 0;
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}
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#ifdef CONFIG_SPL
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u32 spl_boot_device(void)
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{
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#ifdef CONFIG_SPL_MMC_SUPPORT
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return BOOT_DEVICE_MMC1;
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#else
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puts("Unknown boot device\n");
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hang();
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#endif
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}
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#endif
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#ifdef CONFIG_SPL_LOAD_FIT
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int board_fit_config_name_match(const char *name)
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{
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/* boot using first FIT config */
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return 0;
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}
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#endif
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74
board/sifive/fu540/spl.c
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74
board/sifive/fu540/spl.c
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2019 SiFive, Inc
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*
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* Authors:
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* Pragnesh Patel <pragnesh.patel@sifive.com>
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*/
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#include <init.h>
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#include <spl.h>
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#include <misc.h>
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#include <log.h>
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#include <linux/delay.h>
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#include <asm/gpio.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/spl.h>
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#define GEM_PHY_RESET SIFIVE_GENERIC_GPIO_NR(0, 12)
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int init_clk_and_ddr(void)
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{
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int ret;
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ret = soc_spl_init();
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if (ret) {
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debug("FU540 SPL init failed: %d\n", ret);
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return ret;
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}
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/*
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* GEMGXL init VSC8541 PHY reset sequence;
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* leave pull-down active for 2ms
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*/
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udelay(2000);
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ret = gpio_request(GEM_PHY_RESET, "gem_phy_reset");
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if (ret) {
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debug("gem_phy_reset gpio request failed: %d\n", ret);
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return ret;
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}
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/* Set GPIO 12 (PHY NRESET) */
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ret = gpio_direction_output(GEM_PHY_RESET, 1);
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if (ret) {
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debug("gem_phy_reset gpio direction set failed: %d\n", ret);
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return ret;
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}
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udelay(1);
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/* Reset PHY again to enter unmanaged mode */
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gpio_set_value(GEM_PHY_RESET, 0);
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udelay(1);
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gpio_set_value(GEM_PHY_RESET, 1);
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mdelay(15);
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return 0;
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}
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void board_init_f(ulong dummy)
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{
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int ret;
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ret = spl_early_init();
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if (ret)
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panic("spl_early_init() failed: %d\n", ret);
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arch_cpu_init_dm();
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preloader_console_init();
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ret = init_clk_and_ddr();
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if (ret)
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panic("init_clk_and_ddr() failed: %d\n", ret);
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}
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@ -11,6 +11,22 @@
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#include <linux/sizes.h>
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#ifdef CONFIG_SPL
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#define CONFIG_SPL_MAX_SIZE 0x00100000
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#define CONFIG_SPL_BSS_START_ADDR 0x85000000
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#define CONFIG_SPL_BSS_MAX_SIZE 0x00100000
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#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
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CONFIG_SPL_BSS_MAX_SIZE)
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#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000
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#define CONFIG_SPL_LOAD_FIT_ADDRESS 0x84000000
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#define CONFIG_SPL_STACK (0x08000000 + 0x001D0000 - \
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GENERATED_GBL_DATA_SIZE)
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#endif
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#define CONFIG_SYS_SDRAM_BASE 0x80000000
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M)
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/* Environment options */
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#ifndef CONFIG_SPL_BUILD
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#define BOOT_TARGET_DEVICES(func) \
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func(MMC, mmc, 0) \
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func(DHCP, dhcp, na)
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#define CONFIG_PREBOOT \
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"setenv fdt_addr ${fdtcontroladdr};" \
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"fdt addr ${fdtcontroladdr};"
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#endif
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#endif /* __CONFIG_H */
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