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net: gem: Preserve clk on emio interface

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Avoid overwriting GEMx_RCLK_CTRL and GEMx_CLK_CTRL
if the Ethernet interface is connect on EMIO

Do not enable emio for this standard board configuration for now.

Signed-off-by: David Andrey <david.andrey@netmodule.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>
This commit is contained in:
David Andrey 2013-04-05 17:24:24 +02:00 • committed by Michal Simek
parent 117cd4cc10
commit 01fbf31042
3 changed files with 12 additions and 6 deletions
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4
board/xilinx/zynq/board.c
View file

@ -43,11 +43,11 @@ int board_eth_init(bd_t *bis)
#if defined(CONFIG_ZYNQ_GEM) #if defined(CONFIG_ZYNQ_GEM)
# if defined(CONFIG_ZYNQ_GEM0) # if defined(CONFIG_ZYNQ_GEM0)
ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR0, ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR0,
CONFIG_ZYNQ_GEM_PHY_ADDR0); CONFIG_ZYNQ_GEM_PHY_ADDR0, 0);
# endif # endif
# if defined(CONFIG_ZYNQ_GEM1) # if defined(CONFIG_ZYNQ_GEM1)
ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR1, ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR1,
CONFIG_ZYNQ_GEM_PHY_ADDR1); CONFIG_ZYNQ_GEM_PHY_ADDR1, 0);
# endif # endif
#endif #endif
return ret; return ret;

12
drivers/net/zynq_gem.c
View file

@ -33,6 +33,7 @@
#include <phy.h> #include <phy.h>
#include <miiphy.h> #include <miiphy.h>
#include <watchdog.h> #include <watchdog.h>
#include <asm/arch/hardware.h>
#include <asm/arch/sys_proto.h> #include <asm/arch/sys_proto.h>
#if !defined(CONFIG_PHYLIB) #if !defined(CONFIG_PHYLIB)
@ -136,6 +137,7 @@ struct zynq_gem_priv {
u32 rxbd_current; u32 rxbd_current;
u32 rx_first_buf; u32 rx_first_buf;
int phyaddr; int phyaddr;
u32 emio;
int init; int init;
struct phy_device *phydev; struct phy_device *phydev;
struct mii_dev *bus; struct mii_dev *bus;
@ -317,8 +319,11 @@ static int zynq_gem_init(struct eth_device *dev, bd_t * bis)
clk = (5 << 20) | (8 << 8) | (0 << 4) | (1 << 0); clk = (5 << 20) | (8 << 8) | (0 << 4) | (1 << 0);
break; break;
} }
/* FIXME maybe better to define gem address in hardware.h */
zynq_slcr_gem_clk_setup(dev->iobase != 0xE000B000, rclk, clk); /* Change the rclk and clk only not using EMIO interface */
if (!priv->emio)
zynq_slcr_gem_clk_setup(dev->iobase !=
ZYNQ_GEM_BASEADDR0, rclk, clk);
setbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK | setbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
ZYNQ_GEM_NWCTRL_TXEN_MASK); ZYNQ_GEM_NWCTRL_TXEN_MASK);
@ -427,7 +432,7 @@ static int zynq_gem_miiphy_write(const char *devname, uchar addr,
return phywrite(dev, addr, reg, val); return phywrite(dev, addr, reg, val);
} }
int zynq_gem_initialize(bd_t *bis, int base_addr, int phy_addr) int zynq_gem_initialize(bd_t *bis, int base_addr, int phy_addr, u32 emio)
{ {
struct eth_device *dev; struct eth_device *dev;
struct zynq_gem_priv *priv; struct zynq_gem_priv *priv;
@ -444,6 +449,7 @@ int zynq_gem_initialize(bd_t *bis, int base_addr, int phy_addr)
priv = dev->priv; priv = dev->priv;
priv->phyaddr = phy_addr; priv->phyaddr = phy_addr;
priv->emio = emio;
sprintf(dev->name, "Gem.%x", base_addr); sprintf(dev->name, "Gem.%x", base_addr);

2
include/netdev.h
View file

@ -104,7 +104,7 @@ int xilinx_emaclite_initialize(bd_t *bis, unsigned long base_addr,
int txpp, int rxpp); int txpp, int rxpp);
int xilinx_ll_temac_eth_init(bd_t *bis, unsigned long base_addr, int flags, int xilinx_ll_temac_eth_init(bd_t *bis, unsigned long base_addr, int flags,
unsigned long ctrl_addr); unsigned long ctrl_addr);
int zynq_gem_initialize(bd_t *bis, int base_addr, int phy_addr); int zynq_gem_initialize(bd_t *bis, int base_addr, int phy_addr, u32 emio);
/* /*
* As long as the Xilinx xps_ll_temac ethernet driver has not its own interface * As long as the Xilinx xps_ll_temac ethernet driver has not its own interface
* exported by a public hader file, we need a global definition at this point. * exported by a public hader file, we need a global definition at this point.