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nand_spl: p1023rds: wait before enabling DDR controller
We have a requirement to wait a period of time before enabling the DDR controller Signed-off-by: Matthew McClintock <msm@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
This commit is contained in:
parent
8c454047fe
commit
02ea538ce9
2 changed files with 20 additions and 5 deletions
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@ -34,7 +34,8 @@ CFLAGS += -DCONFIG_NAND_SPL
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SOBJS = start.o resetvec.o
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SOBJS = start.o resetvec.o
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COBJS = cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \
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COBJS = cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \
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nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o
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nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o \
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../common.o
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SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
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SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
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OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
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OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
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@ -114,6 +115,9 @@ ifneq ($(OBJTREE), $(SRCTREE))
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$(obj)nand_boot.c:
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$(obj)nand_boot.c:
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@rm -f $(obj)nand_boot.c
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@rm -f $(obj)nand_boot.c
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ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $(obj)nand_boot.c
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ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $(obj)nand_boot.c
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$(obj)../common.c:
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@rm -f $(obj)../common.c
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ln -s $(SRCTREE)/nand_spl/board/freescale/common.c $(obj)../common.c
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endif
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endif
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#########################################################################
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#########################################################################
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@ -25,6 +25,10 @@
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#include <asm/io.h>
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#include <asm/io.h>
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#include <nand.h>
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#include <nand.h>
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#include <asm/fsl_law.h>
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#include <asm/fsl_law.h>
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#include <asm/fsl_ddr_sdram.h>
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#include <asm/global_data.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* Fixed sdram init -- doesn't use serial presence detect. */
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/* Fixed sdram init -- doesn't use serial presence detect. */
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void sdram_init(void)
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void sdram_init(void)
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@ -53,20 +57,27 @@ void sdram_init(void)
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out_be32(&ddr->ddr_wrlvl_cntl, CONFIG_SYS_DDR_WRLVL_CNTL);
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out_be32(&ddr->ddr_wrlvl_cntl, CONFIG_SYS_DDR_WRLVL_CNTL);
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out_be32(&ddr->ddr_cdr1, CONFIG_SYS_DDR_CDR_1);
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out_be32(&ddr->ddr_cdr1, CONFIG_SYS_DDR_CDR_1);
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out_be32(&ddr->ddr_cdr2, CONFIG_SYS_DDR_CDR_2);
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out_be32(&ddr->ddr_cdr2, CONFIG_SYS_DDR_CDR_2);
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out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL);
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/* Set, but do not enable the memory */
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out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL & ~SDRAM_CFG_MEM_EN);
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asm volatile("sync;isync");
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udelay(500);
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/* Let the controller go */
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out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN);
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}
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}
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void board_init_f(ulong bootflag)
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void board_init_f(ulong bootflag)
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{
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{
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u32 plat_ratio, bus_clk;
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u32 plat_ratio;
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ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
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ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
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/* initialize selected port with appropriate baud rate */
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/* initialize selected port with appropriate baud rate */
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plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
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plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
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plat_ratio >>= 1;
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plat_ratio >>= 1;
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bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
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gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
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NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
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NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
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bus_clk / 16 / CONFIG_BAUDRATE);
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gd->bus_clk / 16 / CONFIG_BAUDRATE);
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puts("\nNAND boot... ");
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puts("\nNAND boot... ");
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/* Initialize the DDR3 */
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/* Initialize the DDR3 */
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