mirror of
https://github.com/Fishwaldo/u-boot.git
synced 2025-03-18 13:11:31 +00:00
ARM: DTS: da850: Sync from Linux 4.20
Re-sync with 4.20 due some some natural evolution. Signed-off-by: Adam Ford <aford173@gmail.com>
This commit is contained in:
Adam Ford
Tom Rini
parent
343b606261
commit
031288abe9
1 changed files with 341 additions and 8 deletions
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@ -7,10 +7,19 @@
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include "skeleton.dtsi"
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#include <dt-bindings/interrupt-controller/irq.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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chosen { };
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aliases { };
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memory@c0000000 {
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device_type = "memory";
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reg = <0xc0000000 0x0>;
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};
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arm {
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#address-cells = <1>;
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#size-cells = <1>;
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@ -23,6 +32,25 @@
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reg = <0xfffee000 0x2000>;
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};
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};
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clocks: clocks {
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ref_clk: ref_clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-output-names = "ref_clk";
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};
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sata_refclk: sata_refclk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-output-names = "sata_refclk";
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status = "disabled";
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};
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usb_refclkin: usb_refclkin {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-output-names = "usb_refclkin";
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status = "disabled";
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};
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};
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dsp: dsp@11800000 {
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compatible = "ti,da850-dsp";
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reg = <0x11800000 0x40000>,
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@ -33,6 +61,8 @@
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reg-names = "l2sram", "l1pram", "l1dram", "host1cfg", "chipsig";
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interrupt-parent = <&intc>;
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interrupts = <28>;
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clocks = <&psc0 15>;
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resets = <&psc0 15>;
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status = "disabled";
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};
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soc@1c00000 {
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@ -43,17 +73,57 @@
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ranges = <0x0 0x01c00000 0x400000>;
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interrupt-parent = <&intc>;
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psc0: clock-controller@10000 {
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compatible = "ti,da850-psc0";
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reg = <0x10000 0x1000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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clocks = <&pll0_sysclk 1>, <&pll0_sysclk 2>,
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<&pll0_sysclk 4>, <&pll0_sysclk 6>,
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<&async1_clk>;
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clock-names = "pll0_sysclk1", "pll0_sysclk2",
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"pll0_sysclk4", "pll0_sysclk6",
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"async1";
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};
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pll0: clock-controller@11000 {
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compatible = "ti,da850-pll0";
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reg = <0x11000 0x1000>;
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clocks = <&ref_clk>, <&pll1_sysclk 3>;
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clock-names = "clksrc", "extclksrc";
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pll0_pllout: pllout {
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#clock-cells = <0>;
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};
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pll0_sysclk: sysclk {
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#clock-cells = <1>;
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};
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pll0_auxclk: auxclk {
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#clock-cells = <0>;
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};
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pll0_obsclk: obsclk {
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#clock-cells = <0>;
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};
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};
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pmx_core: pinmux@14120 {
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compatible = "pinctrl-single";
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reg = <0x14120 0x50>;
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#address-cells = <1>;
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#size-cells = <0>;
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#pinctrl-cells = <2>;
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pinctrl-single,bit-per-mux;
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pinctrl-single,register-width = <32>;
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pinctrl-single,function-mask = <0xf>;
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/* pin base, nr pins & gpio function */
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pinctrl-single,gpio-range = <&range 0 17 0x8>,
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<&range 17 8 0x4>,
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<&range 26 8 0x4>,
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<&range 34 80 0x8>,
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<&range 129 31 0x8>;
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status = "disabled";
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range: gpio-range {
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#pinctrl-single,gpio-range-cells = <3>;
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};
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serial0_rtscts_pins: pinmux_serial0_rtscts_pins {
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pinctrl-single,bits = <
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/* UART0_RTS UART0_CTS */
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@ -264,8 +334,41 @@
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usb_phy: usb-phy {
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compatible = "ti,da830-usb-phy";
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#phy-cells = <1>;
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clocks = <&usb_phy_clk 0>, <&usb_phy_clk 1>;
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clock-names = "usb0_clk48", "usb1_clk48";
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status = "disabled";
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};
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usb_phy_clk: usb-phy-clocks {
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compatible = "ti,da830-usb-phy-clocks";
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#clock-cells = <1>;
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clocks = <&psc1 1>, <&usb_refclkin>,
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<&pll0_auxclk>;
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clock-names = "fck", "usb_refclkin", "auxclk";
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};
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ehrpwm_tbclk: ehrpwm_tbclk {
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compatible = "ti,da830-tbclksync";
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#clock-cells = <0>;
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clocks = <&psc1 17>;
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clock-names = "fck";
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};
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div4p5_clk: div4.5 {
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compatible = "ti,da830-div4p5ena";
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#clock-cells = <0>;
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clocks = <&pll0_pllout>;
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clock-names = "pll0_pllout";
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};
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async1_clk: async1 {
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compatible = "ti,da850-async1-clksrc";
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#clock-cells = <0>;
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clocks = <&pll0_sysclk 3>, <&div4p5_clk>;
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clock-names = "pll0_sysclk3", "div4.5";
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};
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async3_clk: async3 {
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compatible = "ti,da850-async3-clksrc";
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#clock-cells = <0>;
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clocks = <&pll0_sysclk 2>, <&pll1_sysclk 2>;
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clock-names = "pll0_sysclk2", "pll1_sysclk2";
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};
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};
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edma0: edma@0 {
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compatible = "ti,edma3-tpcc";
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@ -277,18 +380,21 @@
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#dma-cells = <2>;
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ti,tptcs = <&edma0_tptc0 7>, <&edma0_tptc1 0>;
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power-domains = <&psc0 0>;
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};
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edma0_tptc0: tptc@8000 {
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compatible = "ti,edma3-tptc";
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reg = <0x8000 0x400>;
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interrupts = <13>;
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interrupt-names = "edm3_tcerrint";
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power-domains = <&psc0 1>;
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};
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edma0_tptc1: tptc@8400 {
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compatible = "ti,edma3-tptc";
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reg = <0x8400 0x400>;
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interrupts = <32>;
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interrupt-names = "edm3_tcerrint";
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power-domains = <&psc0 2>;
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};
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edma1: edma@230000 {
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compatible = "ti,edma3-tpcc";
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@ -300,12 +406,14 @@
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#dma-cells = <2>;
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ti,tptcs = <&edma1_tptc0 7>;
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power-domains = <&psc1 0>;
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};
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edma1_tptc0: tptc@238000 {
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compatible = "ti,edma3-tptc";
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reg = <0x238000 0x400>;
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interrupts = <95>;
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interrupt-names = "edm3_tcerrint";
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power-domains = <&psc1 21>;
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};
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serial0: serial@42000 {
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compatible = "ti,da830-uart", "ns16550a";
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@ -313,6 +421,8 @@
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reg-io-width = <4>;
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reg-shift = <2>;
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interrupts = <25>;
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clocks = <&psc0 9>;
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power-domains = <&psc0 9>;
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status = "disabled";
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};
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serial1: serial@10c000 {
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@ -321,6 +431,8 @@
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reg-io-width = <4>;
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reg-shift = <2>;
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interrupts = <53>;
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clocks = <&psc1 12>;
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power-domains = <&psc1 12>;
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status = "disabled";
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};
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serial2: serial@10d000 {
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@ -329,6 +441,8 @@
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reg-io-width = <4>;
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reg-shift = <2>;
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interrupts = <61>;
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clocks = <&psc1 13>;
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power-domains = <&psc1 13>;
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status = "disabled";
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};
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rtc0: rtc@23000 {
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@ -336,6 +450,8 @@
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reg = <0x23000 0x1000>;
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interrupts = <19
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19>;
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clocks = <&pll0_auxclk>;
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clock-names = "int-clk";
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status = "disabled";
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};
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i2c0: i2c@22000 {
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@ -344,6 +460,7 @@
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interrupts = <15>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&pll0_auxclk>;
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status = "disabled";
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};
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i2c1: i2c@228000 {
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@ -352,11 +469,21 @@
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interrupts = <51>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&psc1 11>;
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power-domains = <&psc1 11>;
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status = "disabled";
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};
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clocksource: timer@20000 {
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compatible = "ti,da830-timer";
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reg = <0x20000 0x1000>;
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interrupts = <12>, <13>;
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interrupt-names = "tint12", "tint34";
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clocks = <&pll0_auxclk>;
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};
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wdt: wdt@21000 {
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compatible = "ti,davinci-wdt";
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reg = <0x21000 0x1000>;
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clocks = <&pll0_auxclk>;
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status = "disabled";
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};
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mmc0: mmc@40000 {
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@ -367,12 +494,14 @@
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interrupts = <16>;
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dmas = <&edma0 16 0>, <&edma0 17 0>;
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dma-names = "rx", "tx";
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clocks = <&psc0 5>;
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status = "disabled";
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};
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vpif: video@217000 {
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compatible = "ti,da850-vpif";
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reg = <0x217000 0x1000>;
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interrupts = <92>;
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power-domains = <&psc1 9>;
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status = "disabled";
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/* VPIF capture port */
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@ -395,6 +524,7 @@
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interrupts = <72>;
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dmas = <&edma1 28 0>, <&edma1 29 0>;
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dma-names = "rx", "tx";
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clocks = <&psc1 18>;
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status = "disabled";
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};
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ehrpwm0: pwm@300000 {
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@ -402,6 +532,9 @@
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"ti,am33xx-ehrpwm";
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#pwm-cells = <3>;
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reg = <0x300000 0x2000>;
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clocks = <&psc1 17>, <&ehrpwm_tbclk>;
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clock-names = "fck", "tbclk";
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power-domains = <&psc1 17>;
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status = "disabled";
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};
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ehrpwm1: pwm@302000 {
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@ -409,6 +542,9 @@
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"ti,am33xx-ehrpwm";
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#pwm-cells = <3>;
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reg = <0x302000 0x2000>;
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clocks = <&psc1 17>, <&ehrpwm_tbclk>;
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clock-names = "fck", "tbclk";
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power-domains = <&psc1 17>;
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status = "disabled";
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};
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ecap0: ecap@306000 {
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@ -416,6 +552,9 @@
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"ti,am33xx-ecap";
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#pwm-cells = <3>;
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reg = <0x306000 0x80>;
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clocks = <&psc1 20>;
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clock-names = "fck";
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power-domains = <&psc1 20>;
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status = "disabled";
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};
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ecap1: ecap@307000 {
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@ -423,6 +562,9 @@
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"ti,am33xx-ecap";
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#pwm-cells = <3>;
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reg = <0x307000 0x80>;
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clocks = <&psc1 20>;
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clock-names = "fck";
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power-domains = <&psc1 20>;
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status = "disabled";
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};
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ecap2: ecap@308000 {
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@ -430,6 +572,9 @@
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"ti,am33xx-ecap";
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#pwm-cells = <3>;
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reg = <0x308000 0x80>;
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clocks = <&psc1 20>;
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clock-names = "fck";
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power-domains = <&psc1 20>;
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status = "disabled";
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};
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spi0: spi@41000 {
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@ -442,6 +587,8 @@
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interrupts = <20>;
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dmas = <&edma0 14 0>, <&edma0 15 0>;
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dma-names = "rx", "tx";
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clocks = <&psc0 4>;
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power-domains = <&psc0 4>;
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status = "disabled";
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};
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spi1: spi@30e000 {
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@ -454,6 +601,8 @@
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interrupts = <56>;
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dmas = <&edma0 18 0>, <&edma0 19 0>;
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dma-names = "rx", "tx";
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clocks = <&psc1 10>;
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power-domains = <&psc1 10>;
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status = "disabled";
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};
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usb0: usb@200000 {
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@ -465,6 +614,8 @@
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dr_mode = "otg";
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phys = <&usb_phy 0>;
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phy-names = "usb-phy";
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clocks = <&psc1 1>;
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clock-ranges;
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status = "disabled";
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#address-cells = <1>;
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@ -488,6 +639,7 @@
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interrupts = <58>;
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#dma-cells = <2>;
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#dma-channels = <4>;
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power-domains = <&psc1 1>;
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status = "okay";
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};
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};
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@ -495,13 +647,31 @@
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compatible = "ti,da850-ahci";
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reg = <0x218000 0x2000>, <0x22c018 0x4>;
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interrupts = <67>;
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clocks = <&psc1 8>, <&sata_refclk>;
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clock-names = "fck", "refclk";
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status = "disabled";
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};
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pll1: clock-controller@21a000 {
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compatible = "ti,da850-pll1";
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reg = <0x21a000 0x1000>;
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clocks = <&ref_clk>;
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clock-names = "clksrc";
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pll1_sysclk: sysclk {
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#clock-cells = <1>;
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};
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pll1_obsclk: obsclk {
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#clock-cells = <0>;
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};
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};
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mdio: mdio@224000 {
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compatible = "ti,davinci_mdio";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x224000 0x1000>;
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clocks = <&psc1 5>;
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clock-names = "fck";
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power-domains = <&psc1 5>;
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status = "disabled";
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};
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||||
eth0: ethernet@220000 {
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||||
|
|
@ -517,6 +687,8 @@
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35
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36
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>;
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||||
clocks = <&psc1 5>;
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power-domains = <&psc1 5>;
|
||||
status = "disabled";
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||||
};
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usb1: usb@225000 {
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||||
|
|
@ -525,6 +697,7 @@
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interrupts = <59>;
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phys = <&usb_phy 1>;
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phy-names = "usb-phy";
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clocks = <&psc1 2>;
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status = "disabled";
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};
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gpio: gpio@226000 {
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@ -532,16 +705,169 @@
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x226000 0x1000>;
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interrupts = <42 IRQ_TYPE_EDGE_BOTH
|
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43 IRQ_TYPE_EDGE_BOTH 44 IRQ_TYPE_EDGE_BOTH
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45 IRQ_TYPE_EDGE_BOTH 46 IRQ_TYPE_EDGE_BOTH
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47 IRQ_TYPE_EDGE_BOTH 48 IRQ_TYPE_EDGE_BOTH
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49 IRQ_TYPE_EDGE_BOTH 50 IRQ_TYPE_EDGE_BOTH>;
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interrupts = <42 43 44 45 46 47 48 49 50>;
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ti,ngpio = <144>;
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ti,davinci-gpio-unbanked = <0>;
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clocks = <&psc1 3>;
|
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clock-names = "gpio";
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status = "disabled";
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interrupt-controller;
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#interrupt-cells = <2>;
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gpio-ranges = <&pmx_core 0 15 1>,
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<&pmx_core 1 14 1>,
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<&pmx_core 2 13 1>,
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<&pmx_core 3 12 1>,
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<&pmx_core 4 11 1>,
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<&pmx_core 5 10 1>,
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<&pmx_core 6 9 1>,
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<&pmx_core 7 8 1>,
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<&pmx_core 8 7 1>,
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<&pmx_core 9 6 1>,
|
||||
<&pmx_core 10 5 1>,
|
||||
<&pmx_core 11 4 1>,
|
||||
<&pmx_core 12 3 1>,
|
||||
<&pmx_core 13 2 1>,
|
||||
<&pmx_core 14 1 1>,
|
||||
<&pmx_core 15 0 1>,
|
||||
<&pmx_core 16 39 1>,
|
||||
<&pmx_core 17 38 1>,
|
||||
<&pmx_core 18 37 1>,
|
||||
<&pmx_core 19 36 1>,
|
||||
<&pmx_core 20 35 1>,
|
||||
<&pmx_core 21 34 1>,
|
||||
<&pmx_core 22 33 1>,
|
||||
<&pmx_core 23 32 1>,
|
||||
<&pmx_core 24 24 1>,
|
||||
<&pmx_core 25 22 1>,
|
||||
<&pmx_core 26 21 1>,
|
||||
<&pmx_core 27 20 1>,
|
||||
<&pmx_core 28 19 1>,
|
||||
<&pmx_core 29 18 1>,
|
||||
<&pmx_core 30 17 1>,
|
||||
<&pmx_core 31 16 1>,
|
||||
<&pmx_core 32 55 1>,
|
||||
<&pmx_core 33 54 1>,
|
||||
<&pmx_core 34 53 1>,
|
||||
<&pmx_core 35 52 1>,
|
||||
<&pmx_core 36 51 1>,
|
||||
<&pmx_core 37 50 1>,
|
||||
<&pmx_core 38 49 1>,
|
||||
<&pmx_core 39 48 1>,
|
||||
<&pmx_core 40 47 1>,
|
||||
<&pmx_core 41 46 1>,
|
||||
<&pmx_core 42 45 1>,
|
||||
<&pmx_core 43 44 1>,
|
||||
<&pmx_core 44 43 1>,
|
||||
<&pmx_core 45 42 1>,
|
||||
<&pmx_core 46 41 1>,
|
||||
<&pmx_core 47 40 1>,
|
||||
<&pmx_core 48 71 1>,
|
||||
<&pmx_core 49 70 1>,
|
||||
<&pmx_core 50 69 1>,
|
||||
<&pmx_core 51 68 1>,
|
||||
<&pmx_core 52 67 1>,
|
||||
<&pmx_core 53 66 1>,
|
||||
<&pmx_core 54 65 1>,
|
||||
<&pmx_core 55 64 1>,
|
||||
<&pmx_core 56 63 1>,
|
||||
<&pmx_core 57 62 1>,
|
||||
<&pmx_core 58 61 1>,
|
||||
<&pmx_core 59 60 1>,
|
||||
<&pmx_core 60 59 1>,
|
||||
<&pmx_core 61 58 1>,
|
||||
<&pmx_core 62 57 1>,
|
||||
<&pmx_core 63 56 1>,
|
||||
<&pmx_core 64 87 1>,
|
||||
<&pmx_core 65 86 1>,
|
||||
<&pmx_core 66 85 1>,
|
||||
<&pmx_core 67 84 1>,
|
||||
<&pmx_core 68 83 1>,
|
||||
<&pmx_core 69 82 1>,
|
||||
<&pmx_core 70 81 1>,
|
||||
<&pmx_core 71 80 1>,
|
||||
<&pmx_core 72 70 1>,
|
||||
<&pmx_core 73 78 1>,
|
||||
<&pmx_core 74 77 1>,
|
||||
<&pmx_core 75 76 1>,
|
||||
<&pmx_core 76 75 1>,
|
||||
<&pmx_core 77 74 1>,
|
||||
<&pmx_core 78 73 1>,
|
||||
<&pmx_core 79 72 1>,
|
||||
<&pmx_core 80 103 1>,
|
||||
<&pmx_core 81 102 1>,
|
||||
<&pmx_core 82 101 1>,
|
||||
<&pmx_core 83 100 1>,
|
||||
<&pmx_core 84 99 1>,
|
||||
<&pmx_core 85 98 1>,
|
||||
<&pmx_core 86 97 1>,
|
||||
<&pmx_core 87 96 1>,
|
||||
<&pmx_core 88 95 1>,
|
||||
<&pmx_core 89 94 1>,
|
||||
<&pmx_core 90 93 1>,
|
||||
<&pmx_core 91 92 1>,
|
||||
<&pmx_core 92 91 1>,
|
||||
<&pmx_core 93 90 1>,
|
||||
<&pmx_core 94 89 1>,
|
||||
<&pmx_core 95 88 1>,
|
||||
<&pmx_core 96 158 1>,
|
||||
<&pmx_core 97 157 1>,
|
||||
<&pmx_core 98 156 1>,
|
||||
<&pmx_core 99 155 1>,
|
||||
<&pmx_core 100 154 1>,
|
||||
<&pmx_core 101 129 1>,
|
||||
<&pmx_core 102 113 1>,
|
||||
<&pmx_core 103 112 1>,
|
||||
<&pmx_core 104 111 1>,
|
||||
<&pmx_core 105 110 1>,
|
||||
<&pmx_core 106 109 1>,
|
||||
<&pmx_core 107 108 1>,
|
||||
<&pmx_core 108 107 1>,
|
||||
<&pmx_core 109 106 1>,
|
||||
<&pmx_core 110 105 1>,
|
||||
<&pmx_core 111 104 1>,
|
||||
<&pmx_core 112 145 1>,
|
||||
<&pmx_core 113 144 1>,
|
||||
<&pmx_core 114 143 1>,
|
||||
<&pmx_core 115 142 1>,
|
||||
<&pmx_core 116 141 1>,
|
||||
<&pmx_core 117 140 1>,
|
||||
<&pmx_core 118 139 1>,
|
||||
<&pmx_core 119 138 1>,
|
||||
<&pmx_core 120 137 1>,
|
||||
<&pmx_core 121 136 1>,
|
||||
<&pmx_core 122 135 1>,
|
||||
<&pmx_core 123 134 1>,
|
||||
<&pmx_core 124 133 1>,
|
||||
<&pmx_core 125 132 1>,
|
||||
<&pmx_core 126 131 1>,
|
||||
<&pmx_core 127 130 1>,
|
||||
<&pmx_core 128 159 1>,
|
||||
<&pmx_core 129 31 1>,
|
||||
<&pmx_core 130 30 1>,
|
||||
<&pmx_core 131 20 1>,
|
||||
<&pmx_core 132 28 1>,
|
||||
<&pmx_core 133 27 1>,
|
||||
<&pmx_core 134 26 1>,
|
||||
<&pmx_core 135 23 1>,
|
||||
<&pmx_core 136 153 1>,
|
||||
<&pmx_core 137 152 1>,
|
||||
<&pmx_core 138 151 1>,
|
||||
<&pmx_core 139 150 1>,
|
||||
<&pmx_core 140 149 1>,
|
||||
<&pmx_core 141 148 1>,
|
||||
<&pmx_core 142 147 1>,
|
||||
<&pmx_core 143 146 1>;
|
||||
};
|
||||
psc1: clock-controller@227000 {
|
||||
compatible = "ti,da850-psc1";
|
||||
reg = <0x227000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
clocks = <&pll0_sysclk 2>, <&pll0_sysclk 4>,
|
||||
<&async3_clk>;
|
||||
clock-names = "pll0_sysclk2", "pll0_sysclk4", "async3";
|
||||
assigned-clocks = <&async3_clk>;
|
||||
assigned-clock-parents = <&pll1_sysclk 2>;
|
||||
};
|
||||
pinconf: pin-controller@22c00c {
|
||||
compatible = "ti,da850-pupd";
|
||||
|
|
@ -556,6 +882,7 @@
|
|||
reg-names = "mpu", "dat";
|
||||
interrupts = <54>;
|
||||
interrupt-names = "common";
|
||||
power-domains = <&psc1 7>;
|
||||
status = "disabled";
|
||||
dmas = <&edma0 1 1>,
|
||||
<&edma0 0 1>;
|
||||
|
|
@ -567,6 +894,9 @@
|
|||
reg = <0x213000 0x1000>;
|
||||
interrupts = <52>;
|
||||
max-pixelclock = <37500>;
|
||||
clocks = <&psc1 16>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&psc1 16>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
|
@ -578,6 +908,9 @@
|
|||
reg = <0x68000000 0x00008000>;
|
||||
ranges = <0 0 0x60000000 0x08000000
|
||||
1 0 0x68000000 0x00008000>;
|
||||
clocks = <&psc0 3>;
|
||||
clock-names = "aemif";
|
||||
clock-ranges;
|
||||
status = "disabled";
|
||||
};
|
||||
memctrl: memory-controller@b0000000 {
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue