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Merge branch 'CR_5042_gmac_phy_delay_ds_samin.guo' into 'jh7110-master'

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CR5042： net: phy: motorcomm: add Pad Drive Strength Cfg

See merge request sdk/u-boot!52
This commit is contained in:
andy.hu 2023-05-10 11:55:20 +00:00
commit 040cfd685c
1 changed files with 20 additions and 2 deletions
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22
drivers/net/phy/motorcomm.c
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@ -40,6 +40,7 @@
#define YTPHY_SPEED_MODE 0xc000
#define YTPHY_SPEED_MODE_BIT 14
#define YTPHY_RGMII_SW_DR_MASK GENMASK(5, 4)
#define YTPHY_RGMII_RXC_DR_MASK GENMASK(15, 13)
#define YT8521_EXT_CLK_GATE 0xc
#define YT8521_EN_SLEEP_SW_BIT 15
@ -73,6 +74,12 @@ struct ytphy_reg_field {
const u8 dflt; /* Default value */
};
static const struct ytphy_reg_field ytphy_dr_grp[] = {
{ "rgmii_sw_dr", 2, 4, 0x3},
{ "rgmii_sw_dr_2", 1, 12, 0x0},
{ "rgmii_sw_dr_rxc", 3, 13, 0x3}
};
static const struct ytphy_reg_field ytphy_rxtxd_grp[] = {
{ "rx_delay_sel", 4, 10, 0x0 },
{ "tx_delay_sel_fe", 4, 4, 0xf },
@ -228,9 +235,20 @@ static int ytphy_of_config(struct phy_device *phydev)
ytphy_write_ext(phydev, YTPHY_EXTREG_CHIP_CONFIG, val);
}
/* set drive strenght of rxd/rx_ctl rgmii pad */
val = ytphy_read_ext(phydev, YTPHY_PAD_DRIVES_STRENGTH_CFG);
val |= YTPHY_RGMII_SW_DR_MASK;
for (i = 0; i < ARRAY_SIZE(ytphy_dr_grp); i++) {
cfg = ofnode_read_u32_default(node,
ytphy_dr_grp[i].name, ~0);
cfg = (cfg != -1) ? cfg : ytphy_dr_grp[i].dflt;
/*check the cfg overflow or not*/
cfg = (cfg > ((1 << ytphy_dr_grp[i].size) - 1)) ?
((1 << ytphy_dr_grp[i].size) - 1) : cfg;
val = bitfield_replace(val, ytphy_dr_grp[i].off,
ytphy_dr_grp[i].size, cfg);
}
ytphy_write_ext(phydev, YTPHY_PAD_DRIVES_STRENGTH_CFG, val);
val = ytphy_read_ext(phydev, YTPHY_EXTREG_RGMII_CONFIG1);