mirror of
https://github.com/Fishwaldo/u-boot.git
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arm: mx6: add support for TBS2910 Matrix ARM miniPC
Add initial support for TBS2910 Matrix ARM miniPC. Support includes MMC, Ethernet, UARTs, HDMI, USB, SATA, PCI, I2C, RTC. Signed-off-by: Soeren Moch <smoch@web.de>
This commit is contained in:
Soeren Moch
Stefano Babic
parent
3302c275b3
commit
05d492a323
7 changed files with 683 additions and 0 deletions
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@ -631,6 +631,9 @@ config TARGET_HUMMINGBOARD
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config TARGET_KOSAGI_NOVENA
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bool "Support Kosagi Novena"
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config TARGET_TBS2910
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bool "Support tbs2910"
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config TARGET_TQMA6
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bool "TQ Systems TQMa6 board"
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select CPU_V7
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@ -934,6 +937,7 @@ source "board/sunxi/Kconfig"
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source "board/syteco/jadecpu/Kconfig"
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source "board/syteco/zmx25/Kconfig"
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source "board/taskit/stamp9g20/Kconfig"
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source "board/tbs/tbs2910/Kconfig"
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source "board/ti/am335x/Kconfig"
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source "board/ti/am43xx/Kconfig"
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source "board/ti/ti814x/Kconfig"
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23
board/tbs/tbs2910/Kconfig
Normal file
23
board/tbs/tbs2910/Kconfig
Normal file
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@ -0,0 +1,23 @@
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if TARGET_TBS2910
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config SYS_CPU
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string
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default "armv7"
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config SYS_BOARD
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string
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default "tbs2910"
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config SYS_VENDOR
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string
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default "tbs"
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config SYS_SOC
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string
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default "mx6"
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config SYS_CONFIG_NAME
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string
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default "tbs2910"
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endif
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6
board/tbs/tbs2910/MAINTAINERS
Normal file
6
board/tbs/tbs2910/MAINTAINERS
Normal file
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@ -0,0 +1,6 @@
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TBS2910 BOARD
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M: Soeren Moch <smoch@web.de>
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S: Maintained
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F: board/tbs/tbs2910/
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F: configs/tbs2910_defconfig
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F: include/configs/tbs2910.h
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7
board/tbs/tbs2910/Makefile
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7
board/tbs/tbs2910/Makefile
Normal file
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@ -0,0 +1,7 @@
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#
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# Copyright (C) 2014 Soeren Moch <smoch@web.de>
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y := tbs2910.o
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398
board/tbs/tbs2910/tbs2910.c
Normal file
398
board/tbs/tbs2910/tbs2910.c
Normal file
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@ -0,0 +1,398 @@
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/*
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* Copyright (C) 2014 Soeren Moch <smoch@web.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <asm/arch/clock.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/iomux.h>
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#include <asm/arch/mx6-pins.h>
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#include <asm/errno.h>
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#include <asm/gpio.h>
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#include <asm/imx-common/mxc_i2c.h>
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#include <asm/imx-common/iomux-v3.h>
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#include <asm/imx-common/sata.h>
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#include <asm/imx-common/boot_mode.h>
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#include <asm/imx-common/video.h>
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#include <mmc.h>
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#include <fsl_esdhc.h>
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#include <miiphy.h>
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#include <netdev.h>
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#include <asm/arch/mxc_hdmi.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/io.h>
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#include <asm/arch/sys_proto.h>
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#include <i2c.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define WEAK_PULLUP (PAD_CTL_PUS_47K_UP | \
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PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
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PAD_CTL_SRE_SLOW)
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#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
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PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
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PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
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PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
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PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
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PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
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#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
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PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
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PAD_CTL_ODE | PAD_CTL_SRE_FAST)
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#define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
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#ifdef CONFIG_SYS_I2C
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/* I2C1, SGTL5000 */
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static struct i2c_pads_info i2c_pad_info0 = {
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.scl = {
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.i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | I2C_PAD,
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.gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | I2C_PAD,
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.gp = IMX_GPIO_NR(5, 27)
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},
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.sda = {
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.i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | I2C_PAD,
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.gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | I2C_PAD,
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.gp = IMX_GPIO_NR(5, 26)
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}
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};
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/* I2C2 HDMI */
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static struct i2c_pads_info i2c_pad_info1 = {
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.scl = {
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.i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
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.gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
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.gp = IMX_GPIO_NR(4, 12)
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},
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.sda = {
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.i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
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.gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
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.gp = IMX_GPIO_NR(4, 13)
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}
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};
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/* I2C3, CON11, DS1307, PCIe_SMB */
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static struct i2c_pads_info i2c_pad_info2 = {
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.scl = {
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.i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | I2C_PAD,
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.gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | I2C_PAD,
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.gp = IMX_GPIO_NR(1, 3)
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},
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.sda = {
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.i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | I2C_PAD,
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.gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | I2C_PAD,
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.gp = IMX_GPIO_NR(1, 6)
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}
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};
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#endif /* CONFIG_SYS_I2C */
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static iomux_v3_cfg_t const uart1_pads[] = {
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MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
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};
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static iomux_v3_cfg_t const uart2_pads[] = {
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MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
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};
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static iomux_v3_cfg_t const enet_pads[] = {
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MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
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/* AR8035 PHY Reset */
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MX6_PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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static iomux_v3_cfg_t const pcie_pads[] = {
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/* W_DISABLE# */
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MX6_PAD_KEY_COL4__GPIO4_IO14 | MUX_PAD_CTRL(WEAK_PULLUP),
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/* PERST# */
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MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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int dram_init(void)
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{
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gd->ram_size = 2048ul * 1024 * 1024;
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return 0;
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}
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static void setup_iomux_enet(void)
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{
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imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
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/* Reset AR8035 PHY */
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gpio_direction_output(IMX_GPIO_NR(1, 25) , 0);
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udelay(500);
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gpio_set_value(IMX_GPIO_NR(1, 25), 1);
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}
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static void setup_pcie(void)
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{
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imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads));
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}
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static void setup_iomux_uart(void)
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{
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imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
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imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
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}
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#ifdef CONFIG_FSL_ESDHC
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static iomux_v3_cfg_t const usdhc2_pads[] = {
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MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
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};
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static iomux_v3_cfg_t const usdhc3_pads[] = {
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MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
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};
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static iomux_v3_cfg_t const usdhc4_pads[] = {
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MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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};
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static struct fsl_esdhc_cfg usdhc_cfg[3] = {
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{USDHC2_BASE_ADDR},
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{USDHC3_BASE_ADDR},
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{USDHC4_BASE_ADDR},
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};
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#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 2)
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#define USDHC3_CD_GPIO IMX_GPIO_NR(2, 0)
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int board_mmc_getcd(struct mmc *mmc)
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{
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struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
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int ret = 0;
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switch (cfg->esdhc_base) {
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case USDHC2_BASE_ADDR:
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ret = !gpio_get_value(USDHC2_CD_GPIO);
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break;
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case USDHC3_BASE_ADDR:
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ret = !gpio_get_value(USDHC3_CD_GPIO);
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break;
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case USDHC4_BASE_ADDR:
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ret = 1; /* eMMC/uSDHC4 is always present */
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break;
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}
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return ret;
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}
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int board_mmc_init(bd_t *bis)
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{
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s32 status = 0;
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int i;
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/*
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* (U-boot device node) (Physical Port)
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* mmc0 SD2
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* mmc1 SD3
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* mmc2 eMMC
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*/
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for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
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switch (i) {
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case 0:
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imx_iomux_v3_setup_multiple_pads(
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usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
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gpio_direction_input(USDHC2_CD_GPIO);
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usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
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break;
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case 1:
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imx_iomux_v3_setup_multiple_pads(
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usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
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gpio_direction_input(USDHC3_CD_GPIO);
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usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
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break;
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case 2:
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imx_iomux_v3_setup_multiple_pads(
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usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
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usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
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break;
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default:
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printf("Warning: you configured more USDHC controllers"
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"(%d) then supported by the board (%d)\n",
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i + 1, CONFIG_SYS_FSL_USDHC_NUM);
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return status;
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}
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status |= fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
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}
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return status;
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}
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#endif /* CONFIG_FSL_ESDHC */
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#ifdef CONFIG_VIDEO_IPUV3
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static void do_enable_hdmi(struct display_info_t const *dev)
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{
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imx_enable_hdmi_phy();
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}
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struct display_info_t const displays[] = {{
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.bus = -1,
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.addr = 0,
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.pixfmt = IPU_PIX_FMT_RGB24,
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.detect = detect_hdmi,
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.enable = do_enable_hdmi,
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.mode = {
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.name = "HDMI",
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/* 1024x768@60Hz (VESA)*/
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.refresh = 60,
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.xres = 1024,
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.yres = 768,
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.pixclock = 15384,
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.left_margin = 160,
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.right_margin = 24,
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.upper_margin = 29,
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.lower_margin = 3,
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.hsync_len = 136,
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.vsync_len = 6,
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.sync = FB_SYNC_EXT,
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.vmode = FB_VMODE_NONINTERLACED
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} } };
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size_t display_count = ARRAY_SIZE(displays);
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static void setup_display(void)
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{
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struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
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int reg;
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s32 timeout = 100000;
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enable_ipu_clock();
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imx_setup_hdmi();
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/* set video pll to 455MHz (24MHz * (37+11/12) / 2) */
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reg = readl(&ccm->analog_pll_video);
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reg |= BM_ANADIG_PLL_VIDEO_POWERDOWN;
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writel(reg, &ccm->analog_pll_video);
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reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT;
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reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(37);
|
||||
reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
|
||||
reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(1);
|
||||
writel(reg, &ccm->analog_pll_video);
|
||||
|
||||
writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num);
|
||||
writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom);
|
||||
|
||||
reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN;
|
||||
writel(reg, &ccm->analog_pll_video);
|
||||
|
||||
while (timeout--)
|
||||
if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
|
||||
break;
|
||||
if (timeout < 0)
|
||||
printf("Warning: video pll lock timeout!\n");
|
||||
|
||||
reg = readl(&ccm->analog_pll_video);
|
||||
reg |= BM_ANADIG_PLL_VIDEO_ENABLE;
|
||||
reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS;
|
||||
writel(reg, &ccm->analog_pll_video);
|
||||
|
||||
/* select video pll for ldb_di0_clk */
|
||||
reg = readl(&ccm->cs2cdr);
|
||||
reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK);
|
||||
writel(reg, &ccm->cs2cdr);
|
||||
|
||||
/* select ldb_di0_clk / 7 for ldb_di0_ipu_clk */
|
||||
reg = readl(&ccm->cscmr2);
|
||||
reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
|
||||
writel(reg, &ccm->cscmr2);
|
||||
|
||||
/* select ldb_di0_ipu_clk for ipu1_di0_clk -> 65MHz pixclock */
|
||||
reg = readl(&ccm->chsccdr);
|
||||
reg |= (CHSCCDR_CLK_SEL_LDB_DI0
|
||||
<< MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
|
||||
writel(reg, &ccm->chsccdr);
|
||||
}
|
||||
#endif /* CONFIG_VIDEO_IPUV3 */
|
||||
|
||||
int board_eth_init(bd_t *bis)
|
||||
{
|
||||
setup_iomux_enet();
|
||||
setup_pcie();
|
||||
return cpu_eth_init(bis);
|
||||
}
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
setup_iomux_uart();
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_CMD_BMODE
|
||||
static const struct boot_mode board_boot_modes[] = {
|
||||
/* 4 bit bus width */
|
||||
{"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
|
||||
{"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
|
||||
/* 8 bit bus width */
|
||||
{"emmc", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
|
||||
{NULL, 0},
|
||||
};
|
||||
#endif
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
/* address of boot parameters */
|
||||
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
|
||||
|
||||
#ifdef CONFIG_VIDEO_IPUV3
|
||||
setup_display();
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_I2C
|
||||
setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
|
||||
setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
|
||||
setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
|
||||
#endif
|
||||
#ifdef CONFIG_DWC_AHSATA
|
||||
setup_sata();
|
||||
#endif
|
||||
#ifdef CONFIG_CMD_BMODE
|
||||
add_board_boot_modes(board_boot_modes);
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
puts("Board: TBS2910 Matrix ARM mini PC\n");
|
||||
return 0;
|
||||
}
|
||||
3
configs/tbs2910_defconfig
Normal file
3
configs/tbs2910_defconfig
Normal file
|
|
@ -0,0 +1,3 @@
|
|||
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q2g.cfg,MX6Q"
|
||||
CONFIG_ARM=y
|
||||
CONFIG_TARGET_TBS2910=y
|
||||
242
include/configs/tbs2910.h
Normal file
242
include/configs/tbs2910.h
Normal file
|
|
@ -0,0 +1,242 @@
|
|||
/*
|
||||
* Copyright (C) 2014 Soeren Moch <smoch@web.de>
|
||||
*
|
||||
* Configuration settings for the TBS2910 MatrixARM board.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __TBS2910_CONFIG_H
|
||||
#define __TBS2910_CONFIG_H
|
||||
|
||||
#include "mx6_common.h"
|
||||
#include <asm/arch/imx-regs.h>
|
||||
#include <asm/imx-common/gpio.h>
|
||||
|
||||
/* General configuration */
|
||||
#define CONFIG_MX6
|
||||
#define CONFIG_DISPLAY_CPUINFO
|
||||
#define CONFIG_DISPLAY_BOARDINFO_LATE
|
||||
#define CONFIG_SYS_THUMB_BUILD
|
||||
|
||||
#define CONFIG_MACH_TYPE 3980
|
||||
|
||||
#define CONFIG_CMDLINE_TAG
|
||||
#define CONFIG_SETUP_MEMORY_TAGS
|
||||
#define CONFIG_INITRD_TAG
|
||||
#define CONFIG_REVISION_TAG
|
||||
#define CONFIG_SYS_GENERIC_BOARD
|
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F
|
||||
#define CONFIG_MXC_GPIO
|
||||
#define CONFIG_CMD_GPIO
|
||||
|
||||
#define CONFIG_SYS_LONGHELP
|
||||
#define CONFIG_SYS_HUSH_PARSER
|
||||
#define CONFIG_SYS_PROMPT "Matrix U-Boot> "
|
||||
#define CONFIG_BOOTDELAY 3
|
||||
#define CONFIG_AUTO_COMPLETE
|
||||
#define CONFIG_CMDLINE_EDITING
|
||||
#define CONFIG_SYS_MAXARGS 16
|
||||
#define CONFIG_SYS_CBSIZE 1024
|
||||
#define CONFIG_SYS_PBSIZE \
|
||||
(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
|
||||
#define CONFIG_SYS_HZ 1000
|
||||
|
||||
/* Physical Memory Map */
|
||||
#define CONFIG_NR_DRAM_BANKS 1
|
||||
#define CONFIG_SYS_SDRAM_BASE MMDC0_ARB_BASE_ADDR
|
||||
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET \
|
||||
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_ADDR \
|
||||
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
|
||||
|
||||
#define CONFIG_SYS_MALLOC_LEN (128 * 1024 * 1024)
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
|
||||
#define CONFIG_SYS_MEMTEST_END \
|
||||
(CONFIG_SYS_MEMTEST_START + 500 * 1024 * 1024)
|
||||
|
||||
#define CONFIG_SYS_TEXT_BASE 0x80000000
|
||||
#define CONFIG_SYS_BOOTMAPSZ 0x6C000000
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x10800000
|
||||
|
||||
/* Serial console */
|
||||
#define CONFIG_MXC_UART
|
||||
#define CONFIG_MXC_UART_BASE UART1_BASE /* select UART1/UART2 */
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
|
||||
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
|
||||
#define CONFIG_CONSOLE_MUX
|
||||
#define CONFIG_CONS_INDEX 1
|
||||
|
||||
/* *** Command definition *** */
|
||||
#include <config_cmd_default.h>
|
||||
|
||||
#undef CONFIG_CMD_IMLS
|
||||
|
||||
#define CONFIG_CMD_BMODE
|
||||
#define CONFIG_CMD_SETEXPR
|
||||
#define CONFIG_CMD_MEMTEST
|
||||
#define CONFIG_CMD_TIME
|
||||
|
||||
/* Filesystems / image support */
|
||||
#define CONFIG_CMD_EXT4
|
||||
#define CONFIG_CMD_FAT
|
||||
#define CONFIG_DOS_PARTITION
|
||||
#define CONFIG_EFI_PARTITION
|
||||
#define CONFIG_CMD_FS_GENERIC
|
||||
|
||||
#define CONFIG_OF_LIBFDT
|
||||
#define CONFIG_CMD_BOOTZ
|
||||
#define CONFIG_SUPPORT_RAW_INITRD
|
||||
#define CONFIG_FIT
|
||||
|
||||
/* MMC */
|
||||
#define CONFIG_FSL_ESDHC
|
||||
#define CONFIG_FSL_USDHC
|
||||
#define CONFIG_SYS_FSL_USDHC_NUM 3
|
||||
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC4_BASE_ADDR
|
||||
|
||||
#define CONFIG_MMC
|
||||
#define CONFIG_CMD_MMC
|
||||
#define CONFIG_GENERIC_MMC
|
||||
#define CONFIG_BOUNCE_BUFFER
|
||||
|
||||
/* Ethernet */
|
||||
#define CONFIG_FEC_MXC
|
||||
#define CONFIG_CMD_PING
|
||||
#define CONFIG_CMD_DHCP
|
||||
#define CONFIG_CMD_MII
|
||||
#define CONFIG_CMD_NET
|
||||
#define CONFIG_FEC_MXC
|
||||
#define CONFIG_MII
|
||||
#define IMX_FEC_BASE ENET_BASE_ADDR
|
||||
#define CONFIG_FEC_XCV_TYPE RGMII
|
||||
#define CONFIG_ETHPRIME "FEC"
|
||||
#define CONFIG_FEC_MXC_PHYADDR 4
|
||||
#define CONFIG_PHYLIB
|
||||
#define CONFIG_PHY_ATHEROS
|
||||
|
||||
/* Framebuffer */
|
||||
#define CONFIG_VIDEO
|
||||
#ifdef CONFIG_VIDEO
|
||||
#define CONFIG_VIDEO_IPUV3
|
||||
#define CONFIG_IPUV3_CLK 260000000
|
||||
#define CONFIG_CFB_CONSOLE
|
||||
#define CONFIG_CFB_CONSOLE_ANSI
|
||||
#define CONFIG_VIDEO_SW_CURSOR
|
||||
#define CONFIG_VGA_AS_SINGLE_DEVICE
|
||||
#define CONFIG_VIDEO_BMP_RLE8
|
||||
#define CONFIG_IMX_HDMI
|
||||
#define CONFIG_IMX_VIDEO_SKIP
|
||||
#define CONFIG_CMD_HDMIDETECT
|
||||
#endif
|
||||
|
||||
/* PCI */
|
||||
#define CONFIG_CMD_PCI
|
||||
#ifdef CONFIG_CMD_PCI
|
||||
#define CONFIG_PCI
|
||||
#define CONFIG_PCI_PNP
|
||||
#define CONFIG_PCI_SCAN_SHOW
|
||||
#define CONFIG_PCIE_IMX
|
||||
#define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(7, 12)
|
||||
#endif
|
||||
|
||||
/* SATA */
|
||||
#define CONFIG_CMD_SATA
|
||||
#ifdef CONFIG_CMD_SATA
|
||||
#define CONFIG_DWC_AHSATA
|
||||
#define CONFIG_SYS_SATA_MAX_DEVICE 1
|
||||
#define CONFIG_DWC_AHSATA_PORT_ID 0
|
||||
#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
|
||||
#define CONFIG_LBA48
|
||||
#define CONFIG_LIBATA
|
||||
#endif
|
||||
|
||||
/* USB */
|
||||
#define CONFIG_CMD_USB
|
||||
#ifdef CONFIG_CMD_USB
|
||||
#define CONFIG_USB_EHCI
|
||||
#define CONFIG_USB_EHCI_MX6
|
||||
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
|
||||
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
|
||||
#define CONFIG_USB_STORAGE
|
||||
#define CONFIG_USB_KEYBOARD
|
||||
#ifdef CONFIG_USB_KEYBOARD
|
||||
#define CONFIG_SYS_USB_EVENT_POLL
|
||||
#define CONFIG_SYS_STDIO_DEREGISTER
|
||||
#define CONFIG_PREBOOT "if hdmidet; then usb start; fi"
|
||||
#endif /* CONFIG_USB_KEYBOARD */
|
||||
#endif /* CONFIG_CMD_USB */
|
||||
|
||||
/* RTC */
|
||||
#define CONFIG_CMD_DATE
|
||||
#ifdef CONFIG_CMD_DATE
|
||||
#define CONFIG_CMD_I2C
|
||||
#define CONFIG_RTC_DS1307
|
||||
#define CONFIG_SYS_RTC_BUS_NUM 2
|
||||
#endif
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_CMD_I2C
|
||||
#ifdef CONFIG_CMD_I2C
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_MXC
|
||||
#define CONFIG_SYS_I2C_SPEED 100000
|
||||
#define CONFIG_I2C_EDID
|
||||
#endif
|
||||
|
||||
/* Fuses */
|
||||
#define CONFIG_CMD_FUSE
|
||||
#ifdef CONFIG_CMD_FUSE
|
||||
#define CONFIG_MXC_OCOTP
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_SYS_DCACHE_OFF
|
||||
#define CONFIG_CMD_CACHE
|
||||
#endif
|
||||
|
||||
/* Flash and environment organization */
|
||||
#define CONFIG_SYS_NO_FLASH
|
||||
|
||||
#define CONFIG_ENV_IS_IN_MMC
|
||||
#define CONFIG_SYS_MMC_ENV_DEV 2
|
||||
#define CONFIG_SYS_MMC_ENV_PART 1
|
||||
#define CONFIG_ENV_SIZE (8 * 1024)
|
||||
#define CONFIG_ENV_OFFSET (384 * 1024)
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"bootargs_mmc1=console=ttymxc0,115200 di0_primary console=tty1\0" \
|
||||
"bootargs_mmc2=video=mxcfb0:dev=hdmi,1920x1080M@60 " \
|
||||
"video=mxcfb1:off video=mxcfb2:off fbmem=28M\0" \
|
||||
"bootargs_mmc3=root=/dev/mmcblk0p1 rootwait consoleblank=0 quiet\0" \
|
||||
"bootargs_mmc=setenv bootargs ${bootargs_mmc1} ${bootargs_mmc2} " \
|
||||
"${bootargs_mmc3}\0" \
|
||||
"bootargs_upd=setenv bootargs console=ttymxc0,115200 " \
|
||||
"rdinit=/sbin/init enable_wait_mode=off\0" \
|
||||
"bootcmd_mmc=run bootargs_mmc; mmc dev 2; " \
|
||||
"mmc read 0x10800000 0x800 0x4000; bootm\0" \
|
||||
"bootcmd_up1=load mmc 1 0x10800000 uImage\0" \
|
||||
"bootcmd_up2=load mmc 1 0x10d00000 uramdisk.img; " \
|
||||
"run bootargs_upd; " \
|
||||
"bootm 0x10800000 0x10d00000\0" \
|
||||
"console=ttymxc0\0" \
|
||||
"fan=gpio set 92\0" \
|
||||
"stdin=serial,usbkbd\0" \
|
||||
"stdout=serial,vga\0" \
|
||||
"stderr=serial,vga\0"
|
||||
|
||||
#define CONFIG_BOOTCOMMAND \
|
||||
"mmc rescan; " \
|
||||
"if run bootcmd_up1; then " \
|
||||
"run bootcmd_up2; " \
|
||||
"else " \
|
||||
"run bootcmd_mmc; " \
|
||||
"fi"
|
||||
|
||||
#endif /* __TBS2910_CONFIG_H * */
|
||||
Loading…
Add table
Reference in a new issue